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STULPI01A 数据表(PDF) 15 Page - STMicroelectronics |
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STULPI01A 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 44 page ![]() STULPI01A - STULPI01B Electrical characteristics 15/44 Symbol Parameter Test conditions Min. Typ. Max. Unit High-speed driver tHSR Data rise time 500 ps tHSF Data fall time 500 ps Waveform requirements including jitter Specified by eye pattern (Figure 3) DRHS High-speed data rate 479.76 480.24 Mb/s ULPI interface CLOCK (measured on CLK pin) fSTART_U Frequency (first transition) (1) 54 60 66 MHz fSTEADY_U Frequency (steady state) 59.97 60 60.03 MHz DSTART_U Duty cycle (first transition) 40 50 60 % DSTEADY_U Duty cycle (steady state) (1) 45 50 55 % TSTEADY_U Time to reach steady state frequency and duty cycle after first transition (1) 1.4 ms TJITTER_U Jitter 400 ps tSCLK60OUT Clock start up time Measured from assertion of STP during suspend, or after release of RESETn pin 250 900 µs ULPI control signals (SDR mode) (1) TSC_U Control in setup time CLOAD = 15pF V1V8VIO = 1.65 - 1.95V 6.0 ns THC_U Control in hold time 0.0 ns TDC_U Control output delay 9.0 ns ULPI data signals (SDR mode) (1) TSD_U Data in setup time CLOAD = 15pF V1V8VIO = 1.65 - 1.95V 6.0 ns THD_U Data in hold time 3.0 ns TDD_U Data output delay 9.0 ns 1. Guaranteed by design. Table 7. Switching characteristics (continued) (Over recommended operating conditions unless otherwise noted. All the typical values are referred to TA = 25 °C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF) |
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