数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

STULPI01A 数据表(PDF) 15 Page - STMicroelectronics

部件名 STULPI01A
功能描述  High speed USB On-The-Go ULPI transceiver
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STULPI01A 数据表(HTML) 15 Page - STMicroelectronics

Back Button STULPI01A Datasheet HTML 11Page - STMicroelectronics STULPI01A Datasheet HTML 12Page - STMicroelectronics STULPI01A Datasheet HTML 13Page - STMicroelectronics STULPI01A Datasheet HTML 14Page - STMicroelectronics STULPI01A Datasheet HTML 15Page - STMicroelectronics STULPI01A Datasheet HTML 16Page - STMicroelectronics STULPI01A Datasheet HTML 17Page - STMicroelectronics STULPI01A Datasheet HTML 18Page - STMicroelectronics STULPI01A Datasheet HTML 19Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 44 page
background image
STULPI01A - STULPI01B
Electrical characteristics
15/44
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
High-speed driver
tHSR
Data rise time
500
ps
tHSF
Data fall time
500
ps
Waveform requirements including
jitter
Specified by eye pattern
(Figure 3)
DRHS
High-speed data rate
479.76
480.24
Mb/s
ULPI interface
CLOCK (measured on CLK pin)
fSTART_U
Frequency (first transition)
(1)
54
60
66
MHz
fSTEADY_U
Frequency (steady state)
59.97
60
60.03
MHz
DSTART_U
Duty cycle (first transition)
40
50
60
%
DSTEADY_U Duty cycle (steady state)
(1)
45
50
55
%
TSTEADY_U
Time to reach steady state
frequency and duty cycle after first
transition
(1)
1.4
ms
TJITTER_U
Jitter
400
ps
tSCLK60OUT Clock start up time
Measured from assertion
of STP during suspend, or
after release of RESETn
pin
250
900
µs
ULPI control signals (SDR mode) (1)
TSC_U
Control in setup time
CLOAD = 15pF
V1V8VIO = 1.65 - 1.95V
6.0
ns
THC_U
Control in hold time
0.0
ns
TDC_U
Control output delay
9.0
ns
ULPI data signals (SDR mode) (1)
TSD_U
Data in setup time
CLOAD = 15pF
V1V8VIO = 1.65 - 1.95V
6.0
ns
THD_U
Data in hold time
3.0
ns
TDD_U
Data output delay
9.0
ns
1.
Guaranteed by design.
Table 7.
Switching characteristics (continued)
(Over recommended operating conditions unless otherwise noted. All the typical values are
referred to TA = 25 °C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com