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STULPI01A 数据表(PDF) 23 Page - STMicroelectronics

部件名 STULPI01A
功能描述  High speed USB On-The-Go ULPI transceiver
PDF  44 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STULPI01A 数据表(HTML) 23 Page - STMicroelectronics

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STULPI01A - STULPI01B
Block description
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Low power mode is exited by asserting STP pin high. PLL is started immediately, and when
the clock becomes stable, it is passed on the output of CLK pin. Then after minimum of 5
clock cycles DIR is deasserted and low power mode is exited. SuspendM bit is reset to 1b.
Note:
STP signal must be kept high until the DIR is deasserted, otherwise low power mode will not
be exited.
6.16
Power down mode
Power down mode is entered by asserting the CSn/PWRDN pin high. Internal voltage
regulators are disabled, and the device has minimum possible power consumption.
STULPI01 has no wake-up capability or USB functionality during power down mode. This
mode can be exited by deasserting CSn/PWRDN pin. Voltage regulators will be turned on
and internal power-on-reset circuit will reset the chip to initial state. ULPI interface pins are
in high impedance state during power down mode.
6.17
VIO OFF mode
In case 1V8VIO voltage is below the minimum value, the VIO OFF mode is entered. The
behavior of the device in VIO OFF mode is the same as in power down mode.
6.18
Start-up procedure
6.18.1
ULPI device detection
Link detects ULPI device presence by sampling the DIR signal at the reset time (Figure 8).
The NXT signal is '0' after reset to signalize 8-bit device to link controller. CLK is '1' to
signalize a DDR capable device.
6.18.2
SDR mode selection
The STULPI01 samples the D0 line on the first rising edge of the output clock on the CLK
pin. When the sampled value is '0', the STULPI01 remains in SDR mode.
SDR mode can be selected again only after hardware reset. During software reset mode,
selection is not performed.
Note:
IMPORTANT: The controller must not drive the DATA lines to a value other than 0x00 or
0x01 during the first rising edge of ULPI CLK, otherwise the behavior of the device may be
undefined.
Table 11.
Low power mode
Signal
Map to
Dir
Description
linestate (0)
D0
out
Driven combinatorially from SE receivers
linestate (1)
D1
out
Driven combinatorially from SE receivers
reserved
D2
out
Reserved
INT
D3
out
Active high interrupt indication. Asserted whenever
any unmasked interrupt occurs.



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