STLC5412FN datasheet(15/74 Pages) STMICROELECTRONICS

15 / 74 page

To read a 12 bits message, the difference is:

limited address field:

A7 - A4

extended data field (D11 - D8): A3 - A0.

The Write/Read back indicator doesn‘t exit.

DIGITAL SYSTEM INTERFACE

Two B channels, each at 64 kbit/s and one D chan-

nel at 16 kbit/s form the Basic access data. Basic

access data is transferred on the Digital System In-

terface with several different formats selectable by

means of the configuration register CR1.

The DSI is basically constituted of 5 wires (see

fig.2 and 3):

BCLK

FSa

FSb

bit clock

data input to transmit to the line

data output received from the line

Transmit Frame sync

Receive Frame sync

It is possible to separate the D channel from the B

channels and to transfer it on a separate Digital

Interface constituted of 2 pins:

D channel data input

D channel data ouput

The TDM (Time Division Multiplex) mode uses

the same bit and frame clocks as for the B chan-

nels. The continuous mode uses an internally

generated 16 kHz bit clock output:

DCLK

D channel clock output

For all formats when D channel port is enabled

”continuous mode” is possible. When the D chan-

nel port is enabled in TDM mode, D bits are as-

signed according to the related format on Dx and

Dr .

STLC5412 provides a choice of four multiplexed

formats for the B and D channels data as shown

in fig.2 and 3.

Format 1: the 2B+D data transfer is assigned to

the first 18 bits of the frame on Br and Bx I/0 pins.

Channels are assigned as follows: B1(8 bits),

B2(8 bits), D(2 bits), with the remaining bits ig-

nored until the next Frame sync pulse.

Format 2: the 2B+D data transfer is assigned to

the first 19 bits of the frame on Br and Bx I/O

pins. Channels are assigned as follows: B1(8

bits), D(1 bit), 1 bit ignored, B2(8 bits), D(1 bit),

with the remaining bits ignored until the next

frame sync pulse.

Format 3: B1 and B2 Channels can be inde-

pendently assigned to any 8 bits wide time slot

among 64 (or less) on the Bx and Br pins. The

transmit and receive directions are also inde-

pendent. When TDM mode is selected, the D

channel can be assigned to any 2 bits wide time

slot among 256 on the Bx and Br pins or on the

Dx and Dr pins (D port disabled or enabled in

TDM mode respectively).

Format 4: is a GCI like format excluding Monitor

channel and C/I channel. The 2B+D data transfer

is assigned to the first 26 bits of the frame on Br

and Bx I/O pins. Channels are assigned as fol-

lows. B1(8 bits) B2(8 bits), 8 bits ignored, D(2

bits), with remaining bits ignored up to the next

frame sync pulse.

When the Digital Interface clocks are selected as

inputs, FSa must be a 8 kHz clock input which in-

dicates the start of the frame on the data input pin

Bx. When the Digital Interface clocks are selected

as outputs, FSa is an 8 kHz output pulse con-

forming to

the selected format which indicates

the frame beginning for both Tx and Rx direc-

tions.

When the Digital Interface clocks are selected as

inputs, FSb is a 8 kHz clock input which defines

the start of the frame on the data ouput pin Br.

When the Digital Interface clocks are selected as

outputs, FSb is a 8 kHz output pulse indicating

the second 64kbit/s slot.

Two phase-relations between the rising edge of

FSa/FSb and the first (or second for FSb as out-

put) slot of the frame can be selected depending

on format selected: Delayed timing mode or non

Delayed timing mode.

Non delayed data mode is similar to long frame

timing on the COMBOI/II series of devices: The

first bit of the frame begins nominally coincident

with the rising edge of FSa/b. When output, FSa

is coincident with the first 8 bits wide time-slot

while FSb is coincident with the second 8 bits

wide time-slot. Non delayed mode is not available

in format 2.

Delayed timing mode, which is similar to short

frame sync timing on COMBO I/II, in which the

FSa/b input must be set high at least a half cycle

of BCLK earlier the frame beginning. When out-

put, FSa 1bit wide pulse indicates the first 8 bits

wide time-slot while FSb indicates the second.

Delayed mode is not available in format 4.

2B+D basic access data to transmit to the line

can be shifted in at the BCLK frequency on the

falling edges during the assigned time-slots.

When D channel port is enabled, only B1 & B2

data is shifted in during the assigned time slots. In

format 4, data is shifted in at half the BCLK fre-

quency on the receive falling edges.

2B+ D basic access data received from the line

can be shifted out from the Br output at the BCLK

frequency on the rising edges during the assigned

time-slots. Elsewhere, Br is in the high impedance

state. When the D channel port is enabled, only

B1 & B2 data is shifted out from Br. In Format 4,

data is shifted out at half the BCLK frequency on

the transmit rising edges; there is 1.5 period delay

between the rising transmit edge and the receive

falling edge of BCLK.

STLC5412

15/74

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