STLC5412FN datasheet(48/74 Pages) STMICROELECTRONICS

48 / 74 page

DR5-SR0 Receive D channel Time Slot Assign-

ment

DR5-DR0 and SR1-SR0 bits define the binary

number of the receive D channel time-slot. DR5-

DR0 bits define the binary number of the 8 bits

wide timeslot. Time slot are numbered from 0 to

63. Within this selected time slot., SR1,SR0 bits

define the binary number of the 2 bits wide time-

slot. Sub time-slots are numbered 0 to 3. The reg-

ister content is taken into account at each frame

beginning.

Status Register (STATUS)

(Read only)

After reset: 85H

PWDN

X RXFFU RXFFO TXFFU TXFF O

PWDN Power down

PWDN = 1: UID is in power down state

PWDN = 0: UID is in power up state

RXFFU RX FIFO underflow

RXFFU = 1:The bits rate on Br pin is higher than

the bits rate side line.

RXFFU = 0:The bits rate on Br is in accordance

with the bits rate side line

RXFFO: RX FIFO overflow

RXFFO = 1:The bits rate on Br pin is lower than

the bits rate side line.

RXFFO = 0:The bits rate on Br

pin is in

accordance with the bits rate side

line.

TXFFU TX FIFO underflow

TXFFU = 1: The bits rate on Bx pin is lower than

the bits rate side line.

TXFFU = 0: The bits rate on Bx pin is in

accordance with the bits rate side

line.

TXFFO TX FIFO overflow

TXFFO = 1: The bits rate on Bx pin is higher than

the bits rate side line.

TXFFO = 0: The bits rate on Bx pin is in

accordance with the bits rate side

line.

When one of these four bits is set to 1, Tx FIFO

and/or Rx FIFO is re-adjusted and data is lost. An

interrupt or message is generated if FFIT bit in

CR4 register is set to 1. It is always possible to

read this register by writting STATUS bit = 1 in

RXOH register.

Transmit M4 channel Register (TXM4)

After reset: 7DH

-m42X m43X m44X m45X m46X

m48X

When transmitting SL2/SL3 or SN3, the UID shall

continuously send in the M4 channel field the reg-

ister content to the line once per superframe.

superframe.

m41X, m42X in LT, m47X are activation bits.

These bits are controlled directly by the on chip

activation encoder-decoder. The corresponding

bits in the TXM4 register are not significant.

m45X in NT mode is CS0 bit: this is normally 0

(UID performing warm start). Nevertheless, user

can force CSO to 1 by setting m45X to 1.

When a read back is operated on TXM4, m41x,

m42x in LT, m47x are indicating the current value

of act, dea in LT and uoa/sai bits transmitted to

the line.

Receive spare M4 overhead bits Register

(RXM4) (read only)

After reset: 75H

m41r m42r m43r m44r m45r m46r m47r m48r

RXM4 Register is constituted of 8 bits. When the

line is fully activated (super frame synchronized),

STLC5412 extracts the M4 channel bits. m41 is

the act bit; m42 in NT mode is the dea bit; in NT

m47 is the uoa bit; in LT m47 is the sai bit. These

bits are under the control of the activation se-

quencer. No interrupt cycle is provided for the

RXM4 register when a change on one of the acti-

vation bits is detected; never the less, they are

available in RXM4.

When one of the remaining received spare bits is

validated following the criteria selected in the

Configuration Register OPR, the RXM4 register

content is queued in the interrupt register stack, if

no mask overhead bits is set (see MOB bit in CR4

by writting RXM4 bit = 1 in RXOH register.

Transmit M5

and

channels Register

(TXM56)

After reset: 1FH

m51X m61X m52X febx

febx

m51X, m61X, m52X spare over-head bits are nor-

mally equal to 1. Default value can be changed by

setting the respective bits. These bits are trans-

mitted to the line in SL2/SL3 or SN3 signal.

febx Transmit febe bit control

The febe can be forced to 0 by writing 0 in one of

febx if RFS bit in CR6 register is set to 1. The febe bit

set to zero is sent once to the line in the following

available superframe. After febe transmission, febx

STLC5412

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