STLC5412FN datasheet(25/74 Pages) STMICROELECTRONICS

25 / 74 page

with arbitrary phase.

ELASTIC BUFFERS

The UID buffers the 2B+D data in elastic fifos

which are 3 line-frames deep in each direction.

When the Digital Interface is a timing slave, these

FIFOs compensate for relative jitter and wander

between the Digital Interface and the line. Each

buffer can absorb wander up to 18

µs at 80 KHz

max without ”slip”. This is particulary convenient

for NT1-2 or PABX application in case the local

reference clock is jitterized and wandered relative

to the incoming signal from the line.

DECT SYNCHRONIZATION

In a DECT system the U interface is used for digi-

tal transmission between the base station control-

ler (LT) and the base station (NT). The U inter-

face allows the transmission of 4 DECT channels

through B1, B2 using ADPCM compression. Be-

side the D channel allows the exchange of signal-

ling information between the base station control-

ler (BSC) and the base station (BS).

Seamless handover (for switching the radio-com-

munication from one base station to another) re-

quires additional features in U interface circuit for

base stations synchronisation.

DECT Oriented Features In U Interface

Possibility to measure the round-trip delay be-

tween BSC and BS.

The different delay of each BSC-BS connec-

tion can be compensated in each BS with a

preset counter that is loaded with the delay

value provided by the STLC5412 in the BSC

and sent to the BS via the D channel.

Round trip delay (RTD) measurement allows to

estimate the link delay (SFSrNT-SFSxLT =

RTD/2+Konst) with a total accuracy of +/- 200

nsec when STLC5412 is used both in BSC and

BS. The total accuracy is the sum of two con-

tributions. The process spread on internal

propagation delays (

±166.5ns) and jitter on re-

covered clock in LT (

±32.5ns).

DECT frames synchronisation.

The BSC must synchronise all the BSs con-

nected to itself. A synchronisation pulse DEC-

SYNC is provided by the network to all the

STLC5412 devices in the BSC (LT). The

STLC5412 devices synchronise the 2B1Q

frames on the U link with DECSYNC and send

an EOC message to the corresponding BS

(NT). The STLC5412 in the BS (NT) on recep-

tion of the EOC message provides a pulse to

preset the counter for DECT frame generation.

The jitter related to this pulse is the jitter of the

recovered clock in NT. Maximum jitter guaran-

teed on all ETSI loops is

±130ns.

These two features allow the BSC to generate

synchronous DECT frames (160ms) and multi-

frames with maximum phase difference of

±330ns.

LT DECT MODE

In LT DECT mode the STLC5412 provides round

trip delay estimation with a resolution of +/- 33

nsec. and automatic EOC DECT message trans-

fer for base stations synchronisation.

The DECSYNC pulse is applied to pin SFSx

(CR2.7=0). The DECSYNC period must be multi-

ple of 12ms and in phase with FSa. The SFSx in-

put pulse resets the line frame counter when the

device is in power-up. After power-up, before ac-

tivation, it is suggested to wait for the first avail-

able DECSYNC pulse. If not, the DECSYNC

pulse will generate a jump in the line synchronisa-

tion, that can cause a line deactivation.

Round trip delay estimation procedure

The round trip delay is the delay between

Transmit sync word (ISW) and receive Sync

word on the line. It can be estimated from

three parameters that can be read in internal

registers:

tdd: total digital delay

delay between SFSx and SFSr in steps of 12.5

µsec. It is available in register DBAUD0-4

edd: elastic digital delay

value to add to tdd that takes into account the

internal elastic memory state. It is available in

ced: clock elastic delay

It provides the phase difference between trans-

mit and receive clocks in steps of 65.1 nsec. It

is available in register DTXRX. See Application

Note for use.

DECT EOC message transfer

If CR7.0 = 1 (DECT mode) a synchronisation

pulse on pin SFSx triggers the DECT EOC

message transfer. The message stored in

DECTEOC register is transmitted 3 times in

the EOC channel starting from the 1st avail-

able superframe following the DECSYNC pulse

on the SFSx pin. See Application Note for use.

NT DECT MODE

In NT DECT mode the STLC5412 after recogni-

tion of DECT EOC message stored in DECT EOC

nous with next SFSr edge. In this way the

STLC5412 provides on pin SFSx a pulse used to

resynchronise the DECT frame counter in the

base station.

The LOCK bit in CR7 register can be used to enable

the locking of FSa with SFSr after line is activated.

In particular the FSa rising edge will occur 62.5us

after the SFSr rising edge.

STLC5412

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