STLC5412FN datasheet(27/74 Pages) STMICROELECTRONICS

27 / 74 page

registers description for details. New data written to

any of the overhead bit Transmit Registers is resyn-

chronized internally to the next available complete

superframe or half superframe, as appropriate.

Embedded Operation Channel (EOC)

The eoc channel consists of two complete 12 bits

messages per superframe, distributed through the

M1, M2 and M3 bits of each frame. Each mes-

sage is composed of 3 fields; a 3 bit address

identifying the message destination/origin, a 1 bit

indicator for the data mode i.e. encoded message

or raw data, and an 8 bits information field. The

Control Interface (Microwire or Monitor channel in

GCI) provides access to the complete 12 bits of

every message in TX and RX EOC registers.

When non-auto mode is selected, UID does not in-

terpret the received eoc messages e.g. ”send cor-

rupted CRC”; therefore the appropriate command

instruction must be written to the device e.g. ”set to

one bit CTC in register CR4”. It is possible to select

a transparent transmission mode in which the eoc

channel can be considered as a transparent 2 kbit/s

channel. See OPR register description for details.

When auto-mode is selected in GCI configuration,

UID performs automatic recognition / acknow-

ledgement of the eoc messages sent by the net-

work according to processing defined in ANSI

standard and illustrated in figure 9. When UID rec-

ognizes a message with the appropriate address

and a known command, it performs automatically

the relevant action inside the device and send a

message at the digital interface as appropriate. Ta-

ble 5 gives the list of recognized eoc messages and

associated actions.

When NT-RR-AUTO configuration is selected,

eoc addressing is processed according to appen-

dix E of T1E1.601 standard:

– If address of the eoc message received from

LT is in the range of 2 to 6, UID decrements

address and pass the message onto GCI.

– If address of the eoc message received from

GCI is in the range of 1 to 5, UID increments

address and pass the message onto the line

toward LT.

– If data/msg indicator is set to 0, UID pass

data on transparently with eoc address as de-

scribed above.

M4 channel

M4 bit positions of every frame is a channel in

which are transmitted data bits loaded from the

TXM4 transmit register and from the on-chip acti-

vation sequencer each superframe. On the re-

ceive side, M4 bits from one complete superframe

are first validated and then stored in the RXM4

Receive Register or transmitted to on-chip activa-

tion sequencer. See OPR, TXM4 and RXM4 reg-

isters description for details.

When NT1-AUTO or NT-RR-AUTO mode is se-

lected, bits ps1 and ps2 in M4 channel are con-

trolled directly by biasing input pins ES1 and ES2

respectively. e.g. ps1 is sent continuously to the

line equal 0 when ES1 input is forced at 0 Volt.

Spare M5 and M6 bits

The spare bit positions in the M5 and M6 field

form a channel in which are transmitted data bits

loaded from the TXM56 transmit register. On the

receive side, the spare bits in the M5 and M6

field are first validated and then stored in the

RXM56 receive register. See OPR, TXM56 and

RXM56 registers description for details.

CRC calculation/checking

In transmit direction, an on-chip CRC calculation

circuit automatically generates a checksum of the

2B+D+M4 bits using the specified 12th order

polynomial. Once per superframe, the CRC is

transmitted in the M5 and M6 bit positions. In re-

ceive direction, a checksum is again calculated

on the same bits as they are received and, at the

end of the superframe compared with the re-

ceived CRC. The result of this comparison gener-

ates a ”Far End Block Error” bit (febe) which is

transmitted back towards the other end of the

Line in the next but one superframe and an indi-

cation of Near End Block Error is sent to the sys-

tem by means of Register RXM56. If there is no er-

ror in superframe, febe is set = 1, and if there is one

or more errors, febe is set = 0.

UID also includes two 8 bits Block Error Counters

associated with the febe bits transmitted and re-

ceived. It is then possible to select one Error

Counter per direction or to select only one counter

for both by means of bit C2E in OPR register. Block

error counting is always enabled but it is possible to

disabled the threshold interrupt and/or to en-

able/disable the interrupt issued at each received or

transmitted block error detection. See OPR register

for details.

Loopbacks

Six transparent or non transparent channel loop-

backs are provided by UID. It is therefore possible to

operate any loopback on B1, B2 and D channels line

to line or DSI/GCI to DSI/GCI. Command are

groupedin CR3 register.

In addition to the channel loopbacks in LT modes,

a complete transparent loopback operated at the

transmission side of UID allows the device to acti-

vate through an appropriate sequence with the

complete data stream looped-back to the re-

ceiver. Therefore, most of analog/digital clock and

data recovery circuits are tested. After activation

completed, an AI status indication is reported.

Complete loopback is enabled with ARL command

in TXACT register.

STLC5412

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