STLC5412FN datasheet(55/74 Pages) STMICROELECTRONICS

55 / 74 page

Line Interface Circuit

It is very important, comply with ANSI, ETSI and

French standards, that the recommended line in-

terface circuit should be strictly adhered to. The

channel response and dynamic range of this cir-

cuit have been carefully designed as an integral

part of the overall signal processing system

to ensure that the performance require-

ments are met under all the specified loop

conditions. Deviations from this design are

likely to result in sub-optimal performance

or even total failure of the system on some

types of loops.

Turns Ratio: Np:Ns = 1:1.5.

Secondary Inductance: Lp 27mH.

Max leakage inductance: 100

µH

Winding Resistances: 30 ohms

(2.25Rp + Rs)

> 10 ohms.

Return Loss, at 40 kHz and load of 135 ohms: 26

dB. Saturation characteristics: THD –70dB when

tested with 50mA d.c. through the secondary and

a 40kHz sine-wave injected into the primary at a

level which generates, at the secondary, 5VP-P

(Rload = 135ohms).

List of suppliers:

SHOTT

PULSE ENGINEERING

Table 11.

WINDING

NUMBER OF

TURNS

WIRE GAUGE

1-2

98 Single

#34 AWG

6-5, 8-7

120+120 Bifilar

#36 AWG

3-4

62 Single

#34 AWG

WINDING

INDUCTANCE

RESISTANCE

1-2 + 3-4

12 mH

less than 5

Ω

5-6 + 7-8

27 mH

less than 10

Ω

Board Layout

While the pins of the UID are well protected against

electrical misuse, it is recommended that the stand-

ard CMOS practise, of applying GND to the device

before any other connections are made, should al-

ways be followed. In applications where the printed

circuit card may be plugged into a hot socket with

power and clocks already present, an extra long

ground pin on the connector should be used. Great

care must be taken in the layout of the printed cir-

cuit board in order to preserve the high transmis-

sion performance of the STLC5412. To maximize

performance, do not use the philosophy of separat-

ing analog and digital grounds for chip. All GND

pins should be connected together as close as pos-

sible to the pins, and the VCC pins should be

strapped together. All ground connections to each

device should meet at a common point as close as

possible to the GND pins to prevent the interaction

of ground return currents flowing through a com-

mon bus impedance. Two decoupling capacitors of

µF and 0.1µF should be connected from this

common point to VCC pins as close as possible to

the chip. Taking care with the board layout in the

following ways will also help prevent noise injection

into the receiver frontend and maximize the trans-

mission performances. Keep the crystal oscillator

components away from the receiver inputs and use

a shielded ground plane around these components.

Keep the device, the components connected to

LI+/LI- and the transformer as close possible. Sym-

metrical layout for the line interface is suggested.

98T

120T

62T

1.5:1

DEVICE SIDE

LINE SIDE

Figure 11: Transformer Design.

(secondary)

(primary)

STLC5412

55/74

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