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STLC5412FN 数据表(PDF) 36 Page - STMicroelectronics |
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STLC5412FN 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 74 page ![]() register is required to power up the UID. GCI: when GCI ”NT master of the clocks”configura- tion is selected, UID provides the GCI clocks needed for control channel transfer; PUP control in- struction is provided to the UID by pulling low the Bx data input; STLC5412 then reacts sending GCI clocks. It is possible to operate an automatic power up of the UID when a wake up tone is detected from the line by connecting the LSD output directly to the Bx input. GCI: when NT1-2 or LT configuration is selected (M0 = 0), the UID is powered up after configura- tion setting by the PUP code (0000) on C/I Chan- nel. Power down control A control instruction PDN in ACT register is re- quired to power down the device after a period of activity. PDN forces directly the device to the low power state without sequencing through any of the de-activation states. It should therefore only be used after the UID has been put in the line de- activated state. PDN has no influence on the con- tent of the internal registers, but immediately stops the output clocks when UID is in master mode and in µW/DSI mode. In GCI mode, UID send first two times code DI(1111) on C/I channel before powering down at the end of the assigned GCI channel. The DI code purpose is similar to PDN code but power down state is entered only when the line is entirely deactivated (state H1 or J1). The DI com- mand is recommended. Power up state Power up transition enables all analog and digital circuitry, starts the crystal oscillator and internal clocks. The LSD output is in the high impedance state even if a tone is detected from the line. As for PDN, PUP has no influence on the content of the internal registers Power down state Following a period of activity in the power up state, the power down state may be re-entered as described above. Configuration Registers remain in their current state. PDN and DI have no influence on the content of the internal registers: it is then possible, for instance, after a normal deactivation procedure followed by a power down command, to power up again the device in order to operate di- rectly a Warm Start procedure. ACTIVATION/DEACTIVATION SEQUENCING Activation/deactivation signals onto the line are in accordance with the activation/deactivation state matrix given in Appendix A. CASE OF RESTRICTED ACTIVATION The standard specifies a mode where the U inter- face can be turned on without the need to activate the S/T interface provided this function is supported at both ends of the loop. In this condition Mainte- nance channel is available, typically for setting loop-backs in the NT for error rate testing and other diagnostics. When this mode is enabled, bit M47 on the line in LT to NT direction becomes the uoa bit. Setting UAR activation command in the LT chip will set uoa bit equal zero on the line. Detection of uoa bit equal zero by the NT will inhibit activation of the S/T interface. This results in SN3 signal in the NT to LT direction, which causes generation of UAI indication by the LT U device when superframe synchronized. If during restricted activation operation, a TE starts to try activate the S/T interface by sending info 1, the NT can pass this request to the LT via M47 bit, the sai bit. This bit is set equal one by writing AR command to the Activation Control Register. sai bit received equal one causes gen- eration of an AP indication by the LT U device. RESET OF ACTIVATION/DEACTIVATION STATE MACHINE When the device is either powered-up or down, a control instruction RES resets the activation con- troller ready for a cold start. That feature can be used if the far-end equipment fails to warm start, for example if the line card or NT has been re- placed or if in a regenerator, the loss of synchro- nisation of the second section imply the reset of the first section for a further cold start. The con- figuration registers remain in their selected value. HARDWARE RESET When GCI configuration is selected, pin RES acts as a logical hardware Reset. The device is en- tirely reset including activation/deactivation state machine and configuration registers. Configura- tion pins bias excluding MW define the eventual new configuration. Pin MW must be maintained at the 0 Volt for GCI configuration setting. It is possible to operate a similar ”complete reset” of UID by setting high bit RST in the RXOH com- mand register. In this last case the Control inter- face remains enabled. Refer to User guide for Software reset procedure. QUIET MODE It is possible to force the device in a quiet mode in which UID does not react to any line wake-up tone and LSD pin remains high. There are two STLC5412 36/74 |
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