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STLC5466 数据表(PDF) 68 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 130 page  STLC5466 68/130 VI.41 - Fill Character Register 2 FCR2 (60)H VI.42 - SDRAM Mode Register SDRAMR (72)H When the microprocessor writes in this SDRAM Mode register, the SDRAM controller initializes the SDRAM if the NINIT bit of GCR2 is at 0. When the microprocessor reads this register, the SDRAM controller is not affected. Some parameters are frozen: The option field is: Burst Read and Single Write. The Burst Length is 4. The burst data is addressed in sequential mode The programmable parameters are: The 12-bit word sent by the Multi-HDLC to initialize the SDRAM is: For information: bit15 bit8 bit7 bit0 r e s e r v e d FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 After reset (0000)H FC0/7 : FILL CHARACTER (eight bits) In Transparent Mode M1, two messages are separated by FILL CHARACTERS and the de- tection of one FILL CHARACTER marks the end of a message. bit15 bit8 bit7 bit5 bit4 bit0 T S R Nu NuNuNuNuNuNu LT1 LT0 NuNuNuNu After reset (0030)H LT0/1 : Latency Mode Three configurations are possible: NCAS Latency can be 1, 2 or 3) bit15 bit11 bit8 bit7 bit5 bit4 bit0 Nu Nu Nu Nu 0 0 1 0 0 LT2 LT1 LT0 WT BL2 BL1 BL0 Nu Nu Nu Nu 0 0 1 0 0 0 LT1 LT0 0 0 1 0 Option field: Burst Read and Single Write Latency mode Wrap type Burst Length x x 1 0 0 LT2 LT1 LT0 WT BL2 BL1 BL0 tt LT1 LT0 NCAS Latency 0 0 Not allowed 01 1 10 2 11 3 |
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