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STLC5466 数据表(PDF) 100 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 100 Page - STMicroelectronics |
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100 / 130 page  STLC5466 100/130 1.3 Memory obtained with 2M x 8 SDRAM circuit The Address bits delivered by the Multi-HDLC for 2M x n SDRAM circuits are: ADM11 for Bank select corresponding with A21 delivered by the µP ADM0/10 for Row address inputs corresponding with A10/20 delivered by the µP ADM0/8 for Column address inputs corresponding with A1/9delivered by the µP Figure 1-23: First example, 8Mx16 SDRAM memory organisation Signals A23 A22 Signals A0 NLDS NUDS NCE3 1 1 NCE2 1 0 NCE1 0 1 UDQM 1 0 1 NCE0 0 0 LDQM 0 1 0 0 7 NCE2 NCE1 NCE0 LDQM UDQM NCE3 1 2 6 4 5 3 DM0/7 DM8/15 ADM0/11, NWE, NRAS, NCAS, MCLK are connected to each circuit 2M x 8 circuit: two banks 1Mbyte by bank 2M x16 with 2 circuits |
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