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STLC5466 数据表(PDF) 54 Page - STMicroelectronics

部件名 STLC5466
功能描述  64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PDF  130 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC5466 数据表(HTML) 54 Page - STMicroelectronics

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If 8 bit microprocessor the Data (TMDR Register) is taken into account by the transmitter after writing bits
8 to 15 of this register.
Transmit Monitor Address Register (after reading)
When this register is read by the microprocessor, these different bits mean:
VI.24 - Transmit Monitor Data Register
TMDR (2E)H
L
: Last byte
L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last.
L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the
last.
FABT
: FABT = 1, the current message is aborted by the transmitter.
TIV
: Timer interrupt is Validated
TIV = 1, Time Out alarm generates an interrupt when the timer has expired.
TIV = 0, Time Out alarm is masked.
bit15
bit8
bit7
bit0
0
G0
MA2
MA1
MA0 READ
Nu
Nu
Nu
Nu
TO
ABT
L
NOBT
EXE
IDLE
READ, MA0/2, G0 have same definition as already described for the write register cycle.
IDLE
: When this bit is at “1”, IDLE (all 1’s) is transmitted during the channel validation.
EXE
: EXECUTED
When this status bit is at “1”, the command written previously by the microprocessor has been
executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the
microprocessor.
When this bit is at “0”, the command written previously by the microprocessor has not yet been
executed.
NOBT
: NUMBER OF BYTE which has been transmitted.
NOBT = 1, the first byte is transmitting.
NOB T = 0, the second byte is transmitting, the first byte has been transmitted.
L
: Last byte, this bit is the L bit which has been written by the microprocessor.
ABT
: ABORT
ABT=1, the remote receiver has aborted the current message.
TO
: Time Out one millisecond
TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one
millisecond ago.
bit15
bit8
bit7
bit0
M18
M17
M16
M15
M14
M13
M12
M11
M08
M07
M06
M05
M04
M03
M02
M01
After reset (FFFF)H
M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first.
M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first.



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