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STLC5466 数据表(PDF) 98 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 98 Page - STMicroelectronics |
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98 / 130 page  STLC5466 98/130 1.1 Microprocessor, MHDLC, SDRAM clock distribution Figure 1-20: Ex1; different clocks for Multi-HDLC and µP Figure 1-21: Ex2; synchronous clock for Multi-HDLC and µP External clock generation for Multi-HDLC and SDRAM Multi-HDLC STLC5466 Shared memory SDRAM m P SDRAM bus m P bus CLK MCLK External clock generation for mP MCLK: Master Clock of the Multi-HDLC and CLK Clock of the SDRAM are the same mandatory. Multi-HDLC STLC5466 Shared memory SDRAM Internally 50/2 = 25MHz m P 386EXTB SDRAM bus m P bus CLK MCLK External clock generation 50 MHz MCLK, Master Clock of the Multi-HDLC, Master Clock of the mP and CLK Clock of the SDRAM are the same. |
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