STLC5466 datasheet(58/130 Pages) STMICROELECTRONICS

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STLC5466

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VI.30 - Interrupt Mask Register

IMR (3A)H

RxFWAR : Rx DMA CONTROLLER FIFO WARNING

RxFWAR = 1, Rx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed.

RxFOV

: Rx DMA CONTROLLER FIFO OVERLOAD

RxFOV = 1, Rx DMA CONTROLLER has generated an interrupt, it cannot transfer data from

Rx HDLC to external memory, its fifo is completed.

TxFWAR : Tx DMA CONTROLLER FIFO WARNING

TxFWAR = 1, Tx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed.

TxFOV

: Tx DMA CONTROLLER FIFO OVERLOAD

TxFOV = 1, Tx DMA CONTROLLER has generated an interrupt, it cannot transfer data from

Tx HDLC to external memory, its fifo is completed.

INTFWAR: INTERRUPT CONTROLLER FIFO WARNING

INTFWAR = 1, INTERRUPT CONTROLLER has generated an interrupt, its fifo is 3/4 com-

pleted.

INTFOV

: INTERRUPT CONTROLLER FIFO OVERLOAD

INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer sta-

tus from DMA and GCI controllers to external memory, its internal fifo is completed.

TIM

: TIMER

TIM = 1, the programmable timer has generated an interrupt.

PRSR

: Pseudo Random Sequence Recovered

PRSR = 1,the Pseudo Random Sequence transmitted by the generator has been recovered

by the analyser.

SFCO

: Sequence Fault Counter Overload

SFCO = 1, the Fault Counter has reached the value FFFF(H).

bit15

bit8

bit7

bit0

IM13

IM12

IM11

IM10

IM9

IM8

IM7

IM6

IM5

IM4

IM3

IM2

IM1

IM0

After reset (FFFF)H

IM13/0 : INTERRUPT MASK 0/7

When IM0 = 1, HDLC bit is masked.

When IM1 =1, C/IRX bit is masked.

When IM2 = 1, MRX bit is masked.

When IM3 = 1, MTX bit is masked.

When IM4 = 1, ICOV bit is masked

When IM5 = 1, RxFWAR bit is masked.

When IM6 = 1, RxFOV bit is masked.

When IM7 = 1, TxFWAR bit is masked.

When IM8 = 1, TxFOV bit is masked.

When IM9 = 1, INTFWAR bit is masked.

When IM10 = 1, INTFOV bit is masked.

When IM11 = 1, TIM bit is masked.

When IM12 = 1, PRSR bit is masked.

When IM13 = 1, SFCO bit is masked.

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