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STLC5466 数据表(PDF) 99 Page - STMicroelectronics |
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STLC5466 数据表(HTML) 99 Page - STMicroelectronics |
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99 / 130 page  99/130 STLC5466 1.2 Memory obtained with 1M x16 SDRAM circuit The Address bits delivered by the Multi-HDLC for 1M x n SDRAM circuits are: ADM11 for Bank select corresponding with A20 delivered by the µP ADM0/10 for Row address inputs corresponding with A9/19 delivered by the µP ADM0/7 for Column address inputs corresponding with A1/8 delivered by the µP Figure 1-22: 4Mx16 SDRAM memory organisation Signals A22 A21 Signals A0 (or equivalent) NCE3 1 1 NCE2 1 0 NCE1 0 1 UDQM 1 NCE0 0 0 LDQM 0 0 7 NCE2 NCE1 NCE0 LDQM UDQM NCE3 1 2 6 4 5 3 DM0/7 DM8/15 ADM0/11, NWE, NRAS, NCAS, MCLK are connected to each circuit 1M x 16 circuit two banks 512 Kwords (16 bits) by bank |
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