STPCINDUSTRIAL datasheet(23/55 Pages) STMICROELECTRONICS

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PIN DESCRIPTION

23/55

Issue 1.1

RAS#[3:0]

Row Address Strobe. There are 4 ac-

tive low row address strobe outputs, one each for

each bank of the memory. Each bank contains 4

or 8-Bytes of data. The memory controller allows

half of a bank (4-Bytes) to be populated to enable

memory upgrade at finer granularity.

The RAS# signals drive the SIMMs directly with-

out any external buffering. These pins are always

outputs, but they can also simultaneously be in-

puts, to allow the memory controller to monitor the

value of the RAS# signals at the pins.

CAS#[7:0]

Column Address Strobe. There are 8

active low column address strobe outputs, one

each for each Byte of the memory.

The CAS# signals drive the SIMMs either directly

or through external buffers.

These pins are always outputs, but they can also

simultaneously be inputs, to allow the memory

controller to monitor the value of the CAS# signals

at the pins.

MWE#

Write Enable. Write enable specifies

whether the memory access is a read (MWE# = H)

or a write (MWE# = L). This single write enable

controls all DRAMs. It can be externally buffered

to boost the maximum number of loads (DRAM

chips) supported.

The MWE# signals drive the SIMMs directly with-

out any external buffering.

3.2.4 LOCAL BUS INTERFACE

(Combined with ISA Bus)

PA[21:0]

Memory Address. This is the 22-bit Lo-

cal Bus Address

PD[15:0]

Data Bus. This is the 16-bit bidirectional

Local Bus Data bus.

PRDY#

Ready. This input signals the Local Bus

Ready state.

PWR#1

Memory and I/O Write signal for MS Byte

PWR#0

Memory and I/O Write signal for LS Byte.

PRD#1

Memory and I/O Read signals for MS

Byte

PRD#0

Memory and I/O Read signals for LS Byte.

FCS#[1:0], IOCS#[3:0]

Flash Memory and I/O

Chip select.

3.2.5 ISA BUS INTERFACE

LA[23:17]

Unlatched Address. These unlatched

ISA Bus pins address bits 23-17 on 16-bit devices.

When the ISA bus is accessed by any cycle initiat-

ed from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristated.

SA[19:0]

Unlatched Address. These are the 20

low bits of the system address bus of ISA. These

pins are used as an input when an ISA bus master

owns the bus and are outputs at all other times.

SD[15:0]

I/O Data Bus (ISA). These are the exter-

nal ISA databus pins.

IOCHRDY

IO Channel Ready. IOCHRDY is the IO

channel ready signal of the ISA bus and is driven

as an output in response to an ISA master cycle

targeted to the host bus or an internal register of

the STPC Industrial. The STPC Industrial moni-

tors this signal as an input when performing an

ISA cycle on behalf of the host CPU, DMA master

or refresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Industrial

since the access to the system memory can be

considerably delayed due to CRT refresh or a

write back cycle.

ALE

Address Latch Enable. This is the address

latch enable output of the ISA bus and is asserted

by the STPC Industrial to indicate that LA23-17,

SA19-0, AEN and SBHE# signals are valid. The

ALE is driven high during refresh, DMA master or

an ISA master cycles by the STPC Industrial.

ALE is driven low after reset.

BHE#

System Bus High Enable. This signal, when

asserted, indicates that a data Byte is being trans-

ferred on SD15-8 lines. It is used as an input when

an ISA master owns the bus and is an output at all

other times.

MEMR#

Memory Read. This is the memory read

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

MEMW#

Memory Write. This is the memory write

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

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