STPCINDUSTRIAL datasheet(24/55 Pages) STMICROELECTRONICS

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PIN DESCRIPTION

24/55

Issue 1.1

SMEMR#

System Memory Read. The STPC In-

dustrial generates SMEMR# signal of the ISA bus

only when the address is below one MByte or the

cycle is a refresh cycle.

SMEMW#

System Memory Write. The STPC In-

dustrial generates SMEMW# signal of the ISA bus

only when the address is below one MByte.

IOR#

I/O Read. This is the IO read command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

IOW#

I/O Write. This is the IO write command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

MASTER#

Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

MCS16#

Memory Chip Select16. This is the de-

code of LA23-17 address pins of the ISA address

bus without any qualification of the command sig-

nal lines. MCS16# is always an input. The STPC

Industrial ignores this signal during IO and refresh

cycles.

IOCS16#

IO Chip Select16. This signal is the de-

code of SA15-0 address pins of the ISA address

bus without any qualification of the command sig-

nals. The STPC Industrial does not drive IOCS16#

(similar to PC-AT design). An ISA master access

to an internal register of the STPC Industrial is ex-

ecuted as an extended 8-bit IO cycle.

REF#

Refresh Cycle. This is the refresh command

signal of the ISA bus. It is driven as an output

when the STPC Industrial performs a refresh cycle

on the ISA bus. It is used as an input when an ISA

master owns the bus and is used to trigger a re-

fresh cycle.

The STPC Industrial performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then relin-

quished while the refresh cycle continues on the

ISA bus.

AEN

Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to indi-

cate that a DMA transfer will occur. The enabling

of the signal indicates to IO devices to ignore the

IOR#/IOW# signal during DMA transfers.

IOCHCK#

IO Channel Check. IO Channel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal be-

comes active upon seeing IOCHCK# active if the

corresponding bit in Port B is enabled.

GPIOCS#

I/O General Purpose Chip Select 1.

This output signal is used by the external latch on

ISA bus to latch the data on the SD[7:0] bus. The

latch can be use by PMU unit to control the exter-

nal peripheral devices to power down or any other

desired function.

This pin is also serves as a strap input during re-

set.

RTCRW#

Real Time Clock RW#. This pin is used

as RTCRW#. This signal is asserted for any I/O

write to port 71h.

RTCDS#

Real Time Clock DS. This pin is used as

RTCDS. This signal is asserted for any I/O read to

port 71h.

RTCAS#

Real time clock address strobe. This sig-

nal is asserted for any I/O write to port 70h.

RMRTCCS#

ROM/Real Time clock chip select.

This pin is a multi-function pin. This signal is as-

serted if a ROM access is decoded during a mem-

ory cycle. It should be combined with MEMR# or

MEMW# signals to properly access the ROM.

During an IO cycle, this signal is asserted if ac-

cess to the Real Time Clock (RTC) is decoded. It

should be combined with IOR# or IOW# signals to

properly access the real time clock.

IRQ_MUX[3:0]

Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They are

to be encoded before connection to the STPC In-

dustrial using ISACLK and ISACLKX2 as the input

selection strobes.

Note that IRQ8B, which by convention is connect-

ed to the RTC, is inverted before being sent to the

interrupt controller, so that it may be connected di-

rectly to the IRQ# pin of the RTC.

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