STPC4EDBC datasheet(65/93 Pages) STMICROELECTRONICS

65 / 93 page

DESIGN GUIDELINES

Release 1.5 - January 29, 2002

65/93

6.3. ARCHITECTURE RECOMMENDATIONS

This

section

describes

the

recommend

implementations for the STPC interfaces. For

details,

download

the

Reference

Schematics from the STPC web site.

6.3.1. POWER DECOUPLING

An appropriate decoupling of the various STPC

power pins is mandatory for optimum behaviour.

When insufficient, the integrity of the signals is

deteriorated, the stability of the system is reduced

and EMC is increased.

6.3.1.1. PLL decoupling

This is the most important as the STPC clocks are

generated from a single 14MHz stage using

multiple PLLs which are highly sensitive analog

cells. The frequencies to filter are the 25-50 KHz

range which correspond to the internal loop

bandwidth of the PLL and the 10 to 100 MHz

frequency of the output. PLL power pins can be

tied together to simplify the board layout.

6.3.1.2. Decoupling of 3.3V and Vcore

A power plane for each of these supplies with one

decoupling capacitance for each power pin is the

minimum. The use of multiple capacitances with

values in decade is the best (for example: 10pF,

1nF, 100nF, 10uF), the smallest value, the closest

to the power pin. Connecting the various digital

power planes through capacitances will reduce

furthermore the overall impedance and electrical

noise.

6.3.2. 14MHZ OSCILLATOR STAGE

The 14.31818 MHz oscillator stage can be

implemented

using

quartz,

which

the

preferred and cheaper solution, or using an

external 3.3V oscillator.

The crystal must be used in its series-cut

fundamental mode and not in overtone mode. It

must have an Equivalent Series Resistance (ESR,

sometimes referred to as Rm) of less than 50

Ohms (typically 8 Ohms) and a shunt capacitance

(Co) of less than 7 pF. The balance capacitors of

16 pF must be added, one connected to each pin,

as described in Figure 6-3.

In the event of an external oscillator providing the

master clock signal to the STPC Atlas device, the

LVTTL signal should be connected to XTALI, as

described in Figure 6-3.

As this clock is the reference for all the other on-

chip

generated

clocks,

strongly

recommended to shield this stage, including

the 2 wires going to the STPC balls, in order to

reduce the jitter to the minimum and reach the

optimum system stability.

Figure 6-2. PLL decoupling

VDD_PLL

VSS_PLL

PWR

100nF 47uF

GND

Connections must be as short as possible

Figure 6-3. 14.31818 MHz stage

15pF

XTALO

XTALI

XTALO

XTALI

3.3V

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