STPC4EDBC datasheet(79/93 Pages) STMICROELECTRONICS

79 / 93 page

DESIGN GUIDELINES

Release 1.5 - January 29, 2002

79/93

memory clock input (MCLKI) and any other

component

using

the

memory

clock

are

individually driven from a low skew clock driver

with matched routing lengths. In other words, all

clock line lengths that go from the buffer to the

memory chips (MCLKx) and from the buffer to the

STPC (MCLKI) must be identical.

This is shown in Figure 6-20.

The maximum skew between pins for this part is

250ps. The important factors for the clock buffer

are a consistent drive strength and low skew

between the outputs. The delay through the buffer

is not important so it does not have to be a zero

delay PLL type buffer. The trace lengths from the

clock driver to the DIMM CKn pins should be

matched exactly. Since the propagation speed

can vary between PCB layers, the clocks should

be routed in a consistent way. The routing to the

STPC memory input should be longer by 75 mm to

compensate for the extra clock routing on the

DIMM. Also a 20 pF capacitor should be placed as

near as possible to the clock input of the STPC to

compensate for the DIMM’s higher clock load. The

impedance of the trace used for the clock routing

should be matched to the DIMM clock trace

impedance (60-75 ohms)

.To minimise crosstalk

the clocks should be routed with spacing to

adjacent tracks of at least twice the clock trace

width. For designs which use SDRAMs directly

mounted on the motherboard PCB all the clock

trace lengths should be matched exactly.

Figure 6-19. DIMM placement

DIMM2

DIMM1

STPC

35mm

15mm

10mm

116mm

SDRAM I/F

Figure 6-20. Clock Routing

MCLKO

DIMM CKn input

STPC MCLKI

DIMM CKn input

Low skew clock driver:

L+75mm*

20pF

* No additional 75mm when SDRAM directly soldered on board

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