STPC4EDBC datasheet(17/93 Pages) STMICROELECTRONICS

17 / 93 page

PIN DESCRIPTION

Release 1.5 - January 29, 2002

17/93

PCI_CLKO 33 MHz PCI Output Clock. This is the

master PCI bus clock output.

AD[31:0] PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and the data phase of write transactions. It

is driven by the target during the data phase of

read transactions.

CBE#[3:0]

Bus Commands/Byte Enables. These

are the multiplexed command and byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Consumer-II owns the bus and

outputs when the STPC Consumer-II owns the

bus.

FRAME#

Cycle Frame. This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Consumer-II

owns the PCI bus.

IRDY# Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Consumer-II initiates a bus cycle on the

PCI bus. It is used as an input during the PCI

cycles targeted to the STPC Consumer-II to

determine when the current PCI master is ready to

complete the current transaction.

TRDY#

Target Ready. This is the target ready

signal of the PCI bus. It is driven as an output

when the STPC Consumer-II is the target of the

current bus transaction. It is used as an input

when STPC Consumer-II initiates a cycle on the

PCI bus.

LOCK#

PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

DEVSEL# I/O Device Select. This signal is used

as an input when the STPC Consumer-II initiates

a bus cycle on the PCI bus to determine if a PCI

slave device has decoded itself to be the target of

the current transaction. It is asserted as an output,

either when the STPC Consumer-II is the target of

the current PCI transaction, or when no other

device asserts DEVSEL# prior to the subtractive

decode phase of the current PCI transaction.

STOP#

Stop Transaction. Stop is used to

implement the disconnect, retry and abort protocol

of the PCI bus. It is used as an input for the bus

cycles initiated by the STPC Consumer-II and is

used as an output when a PCI master cycle is

targeted to the STPC Consumer-II.

PAR

Parity Signal Transactions. This is the parity

signal of the PCI bus. This signal is used to

guarantee

even

parity

across

AD[31:0],

CBE#[3:0], and PAR. This signal is driven by the

master during the address phase and data phase

of write transactions. It is driven by the target

during data phase of read transactions (its

assertion is identical to that of the AD bus delayed

by one PCI clock cycle).

SERR#

System Error. This is the system error

signal of the PCI bus. It may, if enabled, be

asserted for one PCI clock cycle if target aborts a

STPC Consumer-II initiated PCI transaction. Its

assertion by either the STPC Consumer-II or by

another PCI bus agent will trigger the assertion of

NMI to the host CPU. This is an open drain output.

PCIREQ#[2:0]

PCI Request. These are the three

external PCI master request pins. They indicates

to the PCI arbiter that external agents desire use

of the bus.

PCIGNT#[2:0] PCI Grant. These pins indicate that

the PCI bus has been granted to the master

requesting it on its PCIREQ#.

PCI_INT#[3:0] PCI Interrupt Request. These are

the PCI bus interrupt signals.

2.2.4. ISA INTERFACE

ISA_CLK, ISA_CLKX2 ISA Clock x1, x2. These

pins generate the Clock signal for the ISA bus and

a Doubled Clock signal. They are also used as the

multiplexer control lines for the Interrupt Controller

Interrupt input lines. ISA_CLK is generated from

either PCICLK/4 or OSC14M/ 2.

OSC14M

ISA bus synchronisation clock Output.

This is the buffered 14.318 MHz clock for the ISA

bus.

LA[23:17] Unlatched Address. When the ISA bus

is active, these pins are ISA Bus unlatched

address for 16-bit devices. When ISA bus is

accessed by any cycle initiated from PCI bus,

these pins are in output mode. When an ISA bus

master owns the bus, these pins are in input

mode.

SA[19:0]

ISA Address Bus. System address bus

of ISA on 8-bit slot. These pins are used as an

input when an ISA bus master owns the bus and

are outputs at all other times.

SD[15:0] I/O Data Bus. These pins are the

external data bus to the ISA bus.

ALE Address Latch Enable. This is the address

latch enable output of the ISA bus and is asserted

by the STPC Consumer-II to indicate that LA23-

17, SA19-0, AEN and SBHE# signals are valid.

The ALE is driven high during refresh, DMA

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