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STPC4EDBC 数据表(PDF) 31 Page - STMicroelectronics

部件名 STPC4EDBC
功能描述  X86 Core PC Compatible Information Appliance System-on-Chip
PDF  93 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPC4EDBC 数据表(HTML) 31 Page - STMicroelectronics

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STRAP OPTIONS
Release 1.5 - January 29, 2002
31/93
3.1.4. CPC STRAP REGISTER 0 CONFIGURATION
Table 3-1. HCLK Frequency Programming
HCLK_Strap
Access = 0022h/0023h
Regoffset = 05Fh
76543210
MD[3}
MD[2]
MD[26]
MD[25]
MD[24]
Rsv
This register defaults to the values sampled on MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-3
MD[3:2] & MD[26:24]
These pins reflect the values sampled on MD[3:2] and
MD[26:24] pins respectively and control the Host clock
frequency synthesizer as shown in Table 3-1
Bits 2-0
Rsv
Reserved
MD[3]
MD[2]
MD[26]
MD[25]
MD[24]
HCLK Speed
00
000
25 MHz
00
001
50 MHz
00
010
60 MHz
00
011
66 MHz
01
001
75 MHz
10
011
90 MHz
11
001
100 MHz



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