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HD6417618 数据表(PDF) 149 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 149 Page - Renesas Technology Corp |
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149 / 646 page ![]() Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 117 of 610 REJ09B0131-0600 Bit Bit Name Initial Value R/W Description 20 19 IWRRD1 IWRRD0 1 1 R/W R/W Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The read and read cycles which are performed consecutively and are accessed to different areas are the target cycle. 000: No idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17 16 IWRRS1 IWRRS0 1 1 R/W R/W Idle Cycles for Read-Read in Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The read and read cycles which are performed consecutively and are accessed to the same area are the target cycle. 000: No idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted |
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