HD6417618 datasheet(152/646 Pages) RENESAS

部件名	HD6417618

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 120 of 610

REJ09B0131-0600

7.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B)

CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register

varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0)

specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the

target area. Specify CSnBCR first, then specify CSnWCR.

Normal Space, Byte-Selection SRAM:

• CS0WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address,

CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn assertion to RD and WEn (BEn) assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

HD6417618 数据表(PDF) 152 Page - Renesas Technology Corp

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