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AT89C51AC3-RDTIM 数据表(PDF) 80 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM 数据表(HTML) 80 Page - ATMEL Corporation |
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80 / 140 page ![]() 80 AT89C51AC3 4383D–8051–02/08 Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42. Machine Cycle Count To compute WD Time-Out, the following formula is applied: Note: Svalue represents the decimal value of (S2 S1 S0) The following table outlines the time-out value for FoscXTAL = 12 MHz in X1 mode Table 43. Time-Out Computation S2 S1 S0 Machine Cycle Count 0 0 0 214 - 1 0 0 1 215 - 1 0 1 0 216 - 1 0 1 1 217 - 1 1 0 0 218 - 1 1 0 1 219 - 1 1 1 0 220 - 1 1 1 1 221 - 1 S2 S1 S0 Fosc = 12 MHz Fosc = 16 MHz Fosc = 20 MHz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 s FTime Out F w d 12 2 14 2 Svalue × ( ) 1 – ( ) × ----------------------------------------------------------------- = – |
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