AT89C51AC3-RDTIM datasheet(92/140 Pages) ATMEL

92 / 140 page

AT89C51AC3

4383D–8051–02/08

Reset Value = 0001 0100b

Not bit addressable

Serial Peripheral Status Register

and Control (SPSCR)

The Serial Peripheral Status Register contains flags to signal the following conditions:

•

Data transfer complete

•

Write collision

•

Inconsistent logic level on SS pin (mode fault error)

Table 49. SPSCR Register

SPSCR - Serial Peripheral Status and Control register (0D5H)

CPOL

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle state.

CPHA

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle

state (see CPOL).

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

SPR1

SPR2

SPR1

SPR0 Serial Peripheral Rate

Invalid

CLK PERIPH /4

CLK PERIPH /8

CLK PERIPH /16

CLK PERIPH /32

CLK PERIPH /64

CLK PERIPH /128

Invalid

SPR0

Bit Number

Bit Mnemonic

Description

SPIF

OVR

MODF

SPTE

UARTM

SPTEIE

MODFIE

Bit

Number

Bit

Mnemonic Description

SPIF

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been

approved by a clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

This bit is cleared when reading or writing SPDATA after reading SPSCR.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

OVR

Overrun Error Flag

- Set by hardware when a byte is received whereas SPIF is set (the previous

received data is not overwritten).

- Cleared by hardware when reading SPSCR

AT89C51AC3-RDTIM 数据表(PDF) 92 Page - ATMEL Corporation

AT89C51AC3-RDTIM 数据表(HTML) 92 Page - ATMEL Corporation

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