AT89C51AC3-RDTIM datasheet(44/140 Pages) ATMEL

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AT89C51AC3

4383D–8051–02/08

Overview of FM0

Operations

Flash Registers (SFR)

The CPU interfaces to the flash memory through the FCON register, AUXR1 register

and FSTA register.

These registers are used to map the column latches, HSB, extra row and EEDATA in

the working data or code space.

FCON Register

Table 13. FCON Register

FCON Register (S:D1h)

Flash Control Register

Reset Value= 0000 0000b

FPL3

FPL2

FPL1

FPL0

FPS

FMOD1

FMOD0

FBUSY

Bit

Number

Bit

Mnemonic Description

7-4

FPL3:0

Programming Launch Command Bits

Write 5Xh followed by AXh to launch the programming according to FMOD1:0.

(see Table 16.)

FPS

Flash Map Program Space

When this bit is set:

The MOVX @DPTR, A instruction writes in the columns latches space

When this bit is cleared:

The MOVX @DPTR, A instruction writes in the regular XDATA memory space

2-1

FMOD1:0

Flash Mode

See Table 16.

FBUSY

Flash Busy

Set by hardware when programming is in progress.

Clear by hardware when programming is done.

Can not be changed by software.

AT89C51AC3-RDTIM 数据表(PDF) 44 Page - ATMEL Corporation

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