AT89C51AC3-RDTIM datasheet(84/140 Pages) ATMEL

84 / 140 page

AT89C51AC3

4383D–8051–02/08

In a Master configuration, the SS line can be used in conjunction with the MODF flag in

the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and

SCK (see Error conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

•

The device is configured as a Master and the SSDIS control bit in SPCON is set.

This kind of configuration can be found when only one Master is driving the network

and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in

the SPSCR will never be set(1).

•

The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This

kind of configuration can happen when the system includes one Master and one

Slave only. Therefore, the device should always be selected and there is no reason

that the Master uses the SS pin to select the communicating Slave device.

Note:

1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in

this mode, the SS is used to start the transmission.

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is con-

trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is

selected from one of seven clock rates resulting from the division of the internal clock by

4, 8, 16, 32, 64 or 128.

Table 46 gives the different clock rates selected by SPR2:SPR1:SPR0.

In Slave mode, the maximum baud rate allowed on the SCK input is limited to Fsys/4

Table 46. SPI Master Baud Rate Selection

SPR2

SPR1

SPR0

Clock Rate

Baud Rate Divisor (BD)

Don’t Use

No BRG

CLK PERIPH /4

CLK PERIPH/8

CLK PERIPH /16

CLK PERIPH /32

CLK PERIPH /64

CLK PERIPH /128

128

Don’t Use

No BRG

AT89C51AC3-RDTIM 数据表(PDF) 84 Page - ATMEL Corporation

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