AT89C51AC3-RDTIM datasheet(60/140 Pages) ATMEL

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AT89C51AC3

4383D–8051–02/08

Serial I/O Port

The AT89C51AC3 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

•

Framing error detection

•

Automatic address recognition

Figure 31. Serial I/O Port Block Diagram

Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Figure 32. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register bit is set.

The software may examine the FE bit after each reception to check for data errors.

Once set, only software or a reset clears the FE bit. Subsequently received frames with

valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the

stop bit instead of the last data bit (See Figure 33. and Figure 34.).

Write SBUF

SBUF

Transmitter

SBUF

Receiver

IB Bus

Mode 0 Transmit

Receive

Shift register

Load SBUF

Read SBUF

SCON reg

Interrupt

Request

Serial Port

TXD

RXD

RB8

TB8

REN

SM2

SM1

SM0/FE

IDL

GF0

GF1

POF

SMOD0

SMOD

To UART framing error control

SM0 to UART mode control

Set FE bit if stop bit is 0 (framing error)

AT89C51AC3-RDTIM 数据表(PDF) 60 Page - ATMEL Corporation

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