21

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

Notes:

1. Default State

2. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1

(WAIT asserted one clock cycle before data is valid) is not supported.

3. Data is not ready when WAIT is asserted.

Figure 10-1. Output Configuration

9.

Burst Configuration Register

B15

0

1

(1)

Synchronous Burst Reads Enabled

Asynchronous Reads Enabled

B14

0

(1)

Four-word Page

B13 - B11:

010

(2)

011

100

101

110

(1)

Clock Latency of Two

Clock Latency of Three

Clock Latency of Four

Clock Latency of Five

Clock Latency of Six

B10

0

1

(1)(3)

WAIT Signal is Asserted Low

WAIT Signal is Asserted High

B9

0

1

(1)

Hold Data for One Clock

Hold Data for Two Clocks

B8

0

1

(1)

WAIT Asserted during Clock Cycle in which Data is Valid

WAIT Asserted One Clock Cycle before Data is Valid

B7

1

(1)

Linear Burst Sequence

B6

0

1

(1)

Burst Starts and Data Output on Falling Clock Edge

Burst Starts and Data Output on Rising Clock Edge

B5 - B4

00

(1)

Reserved for Future Use

B3

0

1

(1)

Wrap Burst Within Burst length set by B2 - B0

Don’t Wrap Accesses Within Burst Length set by B2 - B0

B2 - B0

001

010

011

111

(1)

Four-word Burst

Eight-word Burst

Sixteen-word Burst

Continuous Burst

10. Clock Latency versus Input Clock Frequency

Minimum Clock Latency

(Minimum Number of Clocks Following Address Latch)

Input Clock Frequency

5, 6

≤ 66 MHz

4

≤ 61 MHz

2, 3

≤ 40 MHz

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

CLK

I/00 - I/015

I/00 - I/015

1 CLK

Data Hold

(B9 = 0)

2 CLK

Data Hold

(B9 = 1)