AT52SC1283J datasheet(45/52 Pages) ATMEL

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3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

49. Read Cycle Waveforms

49.1

Read Cycle (1)

(Address Controlled, PCS1 = POE = V

IL, ZZ = PWE = VIH, PUB or/and PLB = VIL)

49.2

Read Cycle (2)

(ZZ = PWE = VIH)

Notes:

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

2. At any given temperature and voltage condition, t

HZ (max) is less than tLZ (min) both for a given device and from device to

device interconnection.

3. Do not access device with cycle timing shorter than t

RC (tWC) for continuous periods > 10 µs.

49.3

Page Read Cycle

(ZZ = PWE = VIH, 16 Words Access)

Notes:

1. t

HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

2. At any given temperature and voltage condition, t

HZ (max) is less than tLZ (min) both for a given device and from device to

device interconnection.

3. Do not access device with cycle timing shorter than t

RC (tWC) for continuous periods > 10 µs.

Address

Data Out

Previous Data Valid

Data Valid

Address

Data Valid

High-Z

PCS1

PUB, PLB

POE

Data Out

High-Z

Data Valid

A4~ A20

PCS1

PUB, PLB

Data Out

A0~ A3

MRC

OLZ

BLZ

PAA

OHZ

BHZ

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