33

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

26. Burst Read Waveform (Clock Latency of 3)

Note:

1. Dashed line reflects a B10 and B8 setting of 0 in the configuration register. Solid line reflects a B10 setting of 1 and B8

setting of 1 in the configuration register.

27. Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 3)

Note:

1. Dashed line reflects a burst configuration register setting of B10 and B8 = 1, B9 = 1.

Solid line reflects a burst configuration register setting of B10 = 1, B9 and B8 = 1

VALID

D13

D14

D15

CE

A0-A22

I/O0-I/O15

AVD

CLK

OE

WAIT

(1)

A

C

DE

F

G

B

HIGH Z

HIGH Z

D16

D18

D17

A0-A22

I/O0-I/O15

AVD

CLK

WAIT

(1)

OE

CE

D13

D14

D15

D16

A9