32

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

25. Burst Read Cycle Waveform

Notes:

1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid

line) shown is for a burst configuration setting of B10 = 1 and B8 = 0.

2. After the high-to-low transition on AVD, AVD may remain low.

24. AC Burst Read Timing Characteristics

Symbol

Parameter

Min

Max

Units

t

CLK

CLK Period

15

ns

CLK High Time

4

ns

t

CKL

CLK Low Time

4

ns

t

CKRT

CLK Rise Time

3.5

ns

CLK Fall Time

3.5

ns

t

ACK

Address Valid to Clock

7

ns

t

AVCK

AVD Low to Clock

7

ns

CE Low to Clock

7

ns

t

CKAV

Clock to AVD High

3

ns

t

QHCK

Output Hold from Clock

3

ns

Address Hold from Clock

8

ns

t

CKRY

Clock to WAIT Delay

13

ns

t

CESAV

CE Setup to AVD

10

ns

Address Valid to AVD

10

ns

t

AHAV

Address Hold From AVD

9ns

t

CKQV

CLK to Data Delay

13

ns

CE High to Output High-Z

10

ns

D15

D13

D16

CE

I/O0-I/O15

A0-A22

AVD

CLK

OE

...

WAIT

D17

... D14

...

...

(1)

(2)