AT52SC1283J datasheet(40/52 Pages) ATMEL

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3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

38. PSRAM Description

The Pseudo-SRAM (PSRAM) is an integrated memory based on a self-refresh DRAM array. It is

designed to be identical in operation and interface to the standard 6T SRAMS. The device is

designed for low standby, low operating current and includes a user configurable low-power

mode. Two chip selects (PCS1 and ZZ) and an output enable (POE) is available to allow for

easy memory expansion. Byte controls (PUB and PLB) allow the upper and lower bytes to be

accessed independently and can also be used to deselect the device. The deep sleep mode

reduces standby current drain while not retaining data in the array.

39. PSRAM Features

• Fast Cycle Times

–T

ACC < 70 ns

• Very Low Standby Current

–I

SB0 < 10 µA

• Very Low Operating Current

– 1.0 mA at 1 µs (Typical)

• Memory Expansion with PCS1 and POE

• TTL Compatible Three-state Output Driver

40. Functional Block Diagram

Precharge Circuit

Clk Gen

PVCC

PGND

Memory Array

Row

Addresses

I/O Circuit

Column select

Data

Cont

Data

Cont

Column Addresses

Data

Cont

Control Logic

I/O8 ~ I/O15

I/O0 ~ I/O7

Row

Select

PCS1

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