LTC4261IGN datasheet(8/32 Pages) LINER

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LTC4261/LTC4261-2

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ADIN (Pin 23/Pin 16): ADC Input. A voltage between 0V

and 2.56V applied to this pin is measured by the on-chip

ADC. Tie to VEE if unused.

ADIN2 (Pin 10/NA): Second ADC Input. Not available on

QFN package.

ADR0, ADR1 (Pins 24, 25/Pins 17, 18): Serial Bus Ad-

dress Inputs. Tying these pins to VEE, OPEN or INTVCC

conﬁgures one of nine possible addresses. See Table 1

in Applications Information.

ALERT (Pin 3/Pin 24): Fault Alert Output. Open-drain

logic output that pulls to VEE when a fault occurs to alert

the host controller. A fault alert is enabled by the ALERT

unused.

DRAIN (Pin 16/Pin 11): Drain Sense Input. Connect an

external 1M resistor between this pin and the drain terminal

(VOUT) of the N-channel FET. When the DRAIN pin volt-

age is less than 1.77V and the GATE pin voltage is above

VZ – 1.2V the power good outputs are asserted after a

delay. The voltage at this pin is internally clamped to 4V.

EN (Pin 26/Pin 19): Device Enable Input. Pull low to enable

the N-channel FET to turn-on after a start-up debounce

delay set by the TMR pin. When this pin is pulled high, the

FET is off. Transitions on this pin will be recorded in the

FAULT register. A high-to-low transition activates the logic

to read the state of the ON pin and clear faults. Requires

external pull-up. Debouncing with an external capacitor

is recommended when used to monitor board present.

Connect to VEE if unused.

Exposed Pad (Pin 25, QFN Only): Exposed Pad may be

left open or connected to device ground (VEE).

FLTIN (Pin 22/NA): General Purpose Fault Input. If this

pin pulls low, the FAULT register bit B7 is latched to “1.”

This pin is used to sense an external fault condition and

its status does not affect the FET control functions of the

LTC4261. Not available on the QFN package. Connect to

INTVCC if unused.

GATE (Pin 15/Pin 10): N-Channel FET Gate Drive Output.

This pin is pulled up by an internal current source IGATE

(11.5µA when the SS pin reaches its clamping voltage).

GATE stays low until VIN and INTVCC cross the UVLO

thresholds, UV and OV conditions are satisiﬁed and an

adjustable timer delay expires. During turn-off, short-

circuit or undervoltage lockout (VIN or INTVCC), a 110mA

pull-down current between GATE and VEE is activated.

INTVCC (Pin 7/Pin 4): Low Voltage (5V) Supply Output.

This is the output of the internal linear regulator with an

internal UVLO threshold of 4.25V. This voltage powers up

the data converter and logic control circuitry. Bypass this

pin with a 0.1µF capacitor to VEE.

ON (Pin 2/Pin 23): On Control Input. A rising edge turns

on the external N-channel FET while a falling edge turns it

off. This pin is also used to conﬁgure the state of the FET

ON register bit D3 in the CONTROL register (and hence

the external FET) at power-up. For example if the ON pin

is tied high, then the register bit D3 goes high one timer

cycle after power-up. Likewise, if the ON pin is tied low,

then the device remains off after power-up until the reg-

ister bit D3 is set high using the I2C bus. A high-to-low

transition on this pin clears faults.

OV (Pin 11/Pin 7): Overvoltage Detection Input. Connect

this pin to an external resistive divider from VEE. If the

voltage at the pin rises above 1.77V, the N-channel FET is

turned off. The overvoltage condition does not affect the

status of the power good outputs. On the QFN package,

this pin is also measured by the on-chip ADC. Connect

to VEE if unused.

PG (Pin 27/Pin 20): Power Good Status Output. This

open-drain pin pulls low and stays latched a timer delay

after the FET is on (when GATE reaches VZ – 1.2V and

DRAIN is within 1.77V of VEE). The power good output is

reset in all GATE pull-down events except an overvoltage

fault. Connect to VEE if unused.

PGI (Pin 1/Pin 22): Power Good Input. This pin along

with the PGI check timer serves as a watchdog to monitor

the power-up of the DC/DC converter. The PGI pin must

be low before the PGI check timer expires, otherwise the

GATE pin pulls down and stays latched and a power bad

fault is logged into the FAULT register. The PGI timer is

started after the second power good is latched and its

delay is equal to four times the start-up debounce delay.

Connect to VEE if unused.

(SSOP/QFN)

PIN FUNCTIONS

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