LTC4261IGN datasheet(22/32 Pages) LINER

22 / 32 page

LTC4261/LTC4261-2

42612fb

Conﬁguring the PGIO Pin

Table 6 describes the possible states of the PGIO pin us-

ing the CONTROL register bits D6 and D7. At power-up

the default state is for the PGIO pin to pull low when

the second power good signal is ready. Other uses for

the PGIO pin are to go high impedence when the sec-

ond power good is ready, a general purpose output and a

general purpose input. When the PGIO pin is conﬁgured

as a general purpose output, the status of bit C6 is sent

out to the pin. When it is conﬁgured as a general pur-

pose input, if the input voltage at PGIO is higher than

1.25V, both bit A6 in the STATUS register and bit B6 in

the FAULT register are set. If the input voltage at PGIO

subsequently drops below 1.25V, bit A6 is cleared. Bit

B6 can be cleared by resetting the FAULT register as de-

scribed previously.

Design Example

As a design example, consider the 200W application with

CL = 330µF as shown in Figure 1. The operating voltage

range is from 43V to 71V with a UV turn-off threshold of

38.5V.

The design ﬂow starts with calculating the maximum in-

put current:

MAX ==

200

where 36V is the minimum input voltage.

The selection of the sense resistor, RS, is determined by

the minimum current limit threshold and maximum input

current:

SENSE MIN

MAX

∆

Ω

()

The inrush current is set to 0.66A using CR:

µF

µA

RAMP

INRUSH

••

330

066

The value of RF and CF are chosen to 1k and 33nF as

discussed previously.

The FET is selected to handle the maximum power dissi-

pation during start-up or an input step. The latter usually

results in a larger power due to summation of the inrush

current charging CL and the load current. For a 36V input

step, the total P2t in the FET is approximated by:

V I

MAX

()

••

where t is the time it takes to charge up CL:

µF

INRUSH

••

330

066

which gives a P2t value of 244W2s.

Now the P2t given by the SOA (safe operating area)

curves of candidate FETs must be lower than 244W2s.

The SOA curves of the IRF1310NS provide for 5A at 50V

(250W) for 10ms, which gives a P2t value of 625W2s and

satisﬁes the requirement.

Sizing R1, R2 and R3 for the required UV and OV thresh-

old voltages:

VUV(RISING) = 43V, VUV(FALLING) = 38.5V, (using

VUVH(TH) = 2.56V and VUVH(TH) = 2.291V)

VOV(RISING) = 72.3V, VOV(FALLING) = 70.7V (using

VOV(TH) = 1.77V rising and 1.7325V falling)

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is recommended. The minimum trace width for 1oz cop-

per foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider is

recommended. Note that 1oz copper exhibits a sheet re-

sistance of about 530µ

Ω/square. Small resistances add

up quickly in high current applications. To improve noise

immunity, put the resistive divider to the UV and OV pins

close to the chip and keep traces to VIN and VEE short.

A 0.1µF capacitor from the UVH or UVL pin (and OV pin

through resistor R2) to VEE helps reject supply noise.

APPLICATIONS INFORMATION

LTC4261IGN 数据表(PDF) 22 Page - Linear Technology

LTC4261IGN 数据表(HTML) 22 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载