LTC4261IGN datasheet(19/32 Pages) LINER

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LTC4261/LTC4261-2

42612fb

Figure 7. Adjustment of Undervoltage Thresholds

for Larger (7a) or Smaller (7b) Hysteresis

present bit A1 and the undervoltage fault bit B1. The

power good signals at PG and PGIO are also reset.

The undervoltage present bit A1 is cleared when the

UVH pin rises above 2.56V and the UVL pin rises above

2.291V +

δVUV. After a delay of tD, the FET will turn on

again unless the undervoltage auto-retry has been dis-

abled by clearing bit D1.

When power is applied to the device, if UVL is below

the 2.291V threshold and UVH is below 2.56V –

δVUV

after INTVCC crosses its undervoltage lock out threshold

(4.25V), an undervoltage fault will be logged in the fault

Because of the compromises of selecting from a table of

discrete resistor values (1% resistors in 2% increments,

0.1% resistors in 1% increments), best possible OV and

UV accuracy is achieved using separate dividers for each

pin. This increases the total number of resistors from

three or four to as many as six, but maximizes accuracy,

greatly simpliﬁes calculations and facilitates running

changes to accommodate multiple standards or custom-

ization without any board changes.

FET Short Fault

A FET short fault will be reported if the data converter mea-

sures a current sense voltage greater than or equal to 2mV

while the FET is turned off. This condition sets the FET

short present bit A5 and the FET short fault bit B5.

Power Bad Fault

After the FET is turned on and the power good outputs

pull PG and PGIO low, a delay timer with duration of 4tD is

started and the level of the PGI pin is checked (Figure 3).

If the PGI pin is pulled below its 1.4V threshold before

the PGI check timer expires, the FET will remain on.

Otherwise, the FET is immediately turned off, the power

good signals are reset and the power bad present bit A3

and the power bad fault bit B3 are set. After the FET is

turned off, the power bad present bit A3 will be cleared.

If the PGI pin is subsequently pulled low, the FET will

remain off unless the power bad auto-retry has been en-

abled by setting bit D4 or the power bad fault bit B3 is

cleared. In either of those two conditions, the FET will

turn on again following a delay of tD and the PGI pin is

checked again as described above.

External Fault Monitors

The FLTIN pin (SSOP only) and the PGIO pin, when con-

ﬁgured as general purpose input, allow monitoring of ex-

ternal fault conditions such as broken fuses. If FLTIN is

pulled below its 1.4V threshold, bit B7 in the FAULT reg-

ister is set. An associated alert bit, C7, is also available

in the ALERT register. When the PGIO pin is conﬁgured

as general purpose input, if the voltage at PGIO is above

1.25V, both bit A6 in the STATUS register and bit B6 in

the FAULT register are set, though there is no alert bit as-

sociated with this fault. The external fault conditions do

not directly affect the GATE control functions.

Fault Alerts

When any of the fault bits in FAULT register B is set, an

optional bus alert can be generated by setting the appropri-

ate bit in the ALERT register C. This allows only selected

faults to generate alerts. At power-up the default state is not

to alert on faults. If an alert is enabled, the corresponding

fault will cause the ALERT pin to pull low. After the bus

master controller broadcasts the alert response address,

the LTC4261/LTC4261-2 will respond with its address on

the SDA line and release ALERT as shown in Figure 14.

If there is a collision between two LTC4261’s responding

with their addresses simultaneously, then the device with

453k

UVL

TURN-ON = 46V

TURN-OFF = 38.5V

HYSTERESIS = 7.5V

–48V RTN

(7a)

–48V INPUT

1.91k

UVH

15k

11.8k

453k

UVH

TURN-ON = 43V

TURN-OFF = 41.2V

HYSTERESIS = 1.8V

–48V RTN

(7b)

–48V INPUT

1.91k

UVL

15k

11.8k

42612 F07

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