LTC4261IGN datasheet(17/32 Pages) LINER

17 / 32 page

LTC4261/LTC4261-2

42612fb

Figure 5. Overcurrent Fault and Auto-Retry

In the case of a low impedance short circuit on the load

side or an input step during battery replacement, cur-

rent overshoot is inevitable. A fast SENSE comparator

with a threshold of 150mV detects the overshoot and

immediately pulls GATE low with a 110mA current. Once

the SENSE voltage drops to 50mV, the current limit loop

takes over and servos the current as previously de-

scribed. If the short-circuit condition lasts longer than

530µs, the FET is shut down and the overcurrent fault is

registered.

In the case of an input step, after an internal clamp pulls the

RAMP pin down to 1.1V, the inrush control circuit takes

over and the current limit loop is disengaged before the

circuit breaker timer expires. From this point on, the device

works as in the initial start-up: VOUT is ramped down at the

rate set by IRAMP and CR followed by GATE pull-up. The

power good signals on the PG and PGIO pins, the TMR

pin, and the SS pin are not interrupted through the input

step sequence. The waveform in Figure 6 shows how the

LTC4261/LTC4261-2 responds to an input step.

Note that the current limit threshold should be set

sufﬁciently high to accommodate the sum of the load

current and the inrush current to avoid engagement of

the current limit loop in the event of an input step. The

maximum value of the inrush current is given by:

INRUSH

LOAD

≤ 08

.•

–

where the 0.8 factor is used as a worst case margin com-

bined with the minumum threshold (45mV).

The active current limit circuit is compensated using the

capacitor CG with a series resistor RG (10Ω) connected

between GATE and VEE, as shown in Figure 1. The sug-

gested value for CG is 50nF. This value should work for

most pass transistors (Q1).

Overvoltage Fault

An overvoltage fault occurs when the OV pin rises above

its 1.77V threshold. This shuts off the pass transistor

immediately, sets the overvoltage present bit A0 and

the overvoltage fault bit B0, and pulls the SS pin down.

Note that the power good signals are not affected by the

overvoltage fault. If the OV pin subsequently falls back

below the threshold, the pass transistor will be allowed

TMR

GATE

VOUT

SENSE

PGIO

OC COOLING DELAY

PWRGD1

DELAY

VZ – 1.2V

1.77V

INRUSH

PWRGD2

DELAY

50mV

530

µs

42612 F05

APPLICATIONS INFORMATION

LTC4261IGN 数据表(PDF) 17 Page - Linear Technology

LTC4261IGN 数据表(HTML) 17 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载