LTC4261IGN datasheet(26/32 Pages) LINER

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LTC4261/LTC4261-2

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(DMY) to measure the internal clock cycle (i.e., the serial

data rate). Following the DMY bit are two channel code bits

CH1 and CH0 labeling the ADC channel (see Table 10). Ten

data bits of the ADC channel (ADC9-0) and three FAULT

(PRTY) ends each data stream. After that the SDAO line

enters the idle mode with SDAO pulled high.

The following data reception procedure is recommended:

0. Wait for INTVCC rising edge.

1. Wait for SDAO falling edge.

2. The ﬁrst falling edge could be a glitch, so check again

after a delay of 10µs. If back to high, wait again. If still

low, it is the START bit.

3. Use the following low-to-high and high-to-low transis-

tions to measure 1/2 of the internal clock cycle.

4. Wait for the second low-to-high transistion (middle of

DMY bit).

5. Wait 3/4 of a clock cycle.

6. Sample bit CH1, wait for transistion.

7. Wait 3/4 of a clock cycle.

8. Sample bit CH0, wait for transistion.

9. Wait 3/4 of a clock cycle.

10. Sample ADC9, wait for transistion.

11. Continue until all bits are read.

The above procedure can be ported to a microcontroller

or used to design a state machine in FPGA. Code should

have timeouts in case an edge is missed. Abort the read

if it takes more than double the typical time (1.2ms) for

all 18 bits to be clocked out.

A typical application circuit with the LTC4261/LTC4261-2

in the broadcast mode is illustrated in Figure 17, where

input voltage, VDS of the FET and VSENSE are monitored.

The register addresses and contents are summerized in

Table 1 and Table 2. The function of each register bit is

detailed in Tables 3 to 9.

APPLICATIONS INFORMATION

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