LTC2925

8

2925f

Tracking Cell

The LTC2925’s operation is based on the tracking cell shown

in Figure 5, which uses a proprietary wide-range current

mirror. The tracking cell shown in Figure 5 servos the

TRACK pin at 0.8V. The current supplied by the TRACK pin

is mirrored at the FB pin to establish a voltage at the output

of the slave supply. The slave output voltage varies with

the master signal, enabling the slave supply to be con-

trolled as a function of the master signal with terms set by

1 to 4.

APPLICATIO S I FOR ATIO

In a properly designed system, when the master signal has

reached its maximum voltage the current from the TRACK1

pin is zero. In this case, there is no current from the FB1 pin

and the LTC2925 has no effect on the output voltage accu-

racy, transient response or stability of the slave supply.

cally 1.225V, the GATE pin pulls down with 10

µA and the

master signal and the slave supplies will fall at the same

rate as they rose previously.

The ON pin can be controlled by a digital I/O pin or it can

be used to monitor an input supply. By connecting a resis-

tive divider from an input supply to the ON pin, the supplies

will ramp up only after the monitored supply has reached

a preset voltage.

Controlling the Ramp-Up and Ramp-Down Behavior

The operation of the LTC2925 is most easily understood

by referring to the simplified functional diagram in

Figure 6. When the ON pin is low, the GATE pin is pulled to

ground causing the master signal to remain low. Since the

signal is low, the current from FB1 is also at its maximum.

This current drives the slave’s output to its minimum

voltage.

When the ON pin rises above 1.23V, the master signal

rises and the slave supply tracks the master signal. The

ramp rate is set by an external capacitor driven by a 10

µA

current source from an internal charge pump. If no exter-

nal FET is used, the ramp rate is set by tying the RAMP and

GATE pins together at one terminal of the external capaci-

tor (see the Ratiometric Tracking Example).

Figure 6. Simplified Functional Block Diagram

Figure 5. Simplified Tracking Cell

–

+

FB

TRACK

MASTER

0.8V

2925 F05

SLAVE

DC/DC

+

–

FB OUT

1.2V

–

+

–

+

–

+

GATE

Q1

MASTER

SLAVE1

1.2V

ON

RAMPBUF

10

µA

10

µA

50

µA

2

µA

RAMP

FB1

TRACK1

0.8V

DC/DC

2925 F06

1

×

50mV

SENSEN

SENSEP

SENSEP – SENSEN > 50mV

SCTMR