LTC2925

9

2925f

Optional External FET

Figure 7 illustrates how an optional external N-channel FET

can ramp up a single supply that becomes the master

signal. When used, the FET’s gate is tied to the GATE pin

and its source is tied to the RAMP pin. Under normal op-

eration, the GATE pin sources or sinks 10

µA to ramp the

FET’s gate up or down at a rate set by the external capacitor

connected to the GATE pin.

The series FET easily controls any supply with an output

section for examples.

APPLICATIO S I FOR ATIO

The short-circuit timer duration is configured by a capaci-

tor tied between SCTMR and GND. SCTMR will pull up with

50

µAwhenSENSEP–SENSEN>50mV.Otherwise,itpulls

down with 2

µA.WhenthevoltageatSCTMRexceeds1.23V,

the GATE will be pulled to ground with 20mA and the FAULT

is determined from:

C

At

V

SCTMR

SCTMR

=

50

123

µ •

.

Because the slave supplies track the RAMP pin which is

driven by the external FET, they are pulled low by the track-

ing circuit when a short-circuit fault occurs. Following a

short-circuit fault, the FET is latched off and FAULT is

pulled low until the fault is cleared by pulling the ON pin

below 0.4V. Note that the supplies will not be allowed to

ramp up again until SCTMR has been pulled below about

100mV by the 2

µA pull down current source. The elec-

tronic circuit breaker supports any supply voltage between

rent through the optional series FET, it is capable of moni-

toring other currents, including the current from a slave

supply. The Typical Applications section shows one such

example.

If the electronic circuit breaker is not used, tie SENSEP and

Power Good Timeout

The power good timeout circuit turns off the supplies if an

external supply monitor, connected to the PGI pin, fails to

indicate that all supplies have entered regulation in time

after power up begins. After power up is complete, it turns

off the supplies if any supply exits regulation.

The power good timer duration is configured by a capaci-

tor tied between PGTMR and GND. PGTMR will pull up the

driven above 1.23V. Once the voltage at the PGTMR ex-

ceeds 1.23V, a fault will trip if the PGI pin is low. When the

power good timeout circuit detects a fault, the GATE pin is

Q1

0.1

µF

10k

3.3V

3.3V

2.5V

SLAVE2

MASTER

RAMPBUF

TRACK1

TRACK2

TRACK3

FB2

GATE

LTC2925

PGTMR

SDTMR

SCTMR

GND

2925 F07

RAMP

1.5V

SLAVE3

DC/DC

IN

FB = 0.8V

OUT

DC/DC

IN

FB = 0.8V

RUN/SS

RUN/SS

OUT

FB3

3.3V

PGI

1.8V

SLAVE1

SUPPLY

MONITOR

DC/DC

IN

FB = 1.235V

RUN/SS

OUT

FB1

FAULT

ON

10k

STATUS

REMOTE

RST

SD3

SD2

SD1

10

Ω

Figure 7. Typical Application With External FET

Electronic Circuit Breaker

The LTC2925 features an electronic circuit breaker func-

tion that protects the optional series FET against short

circuits. An external sense resistor is used to measure the

current flowing in the FET. If the voltage across the sense

resistor exceeds 50mV for more than a short-circuit timer

cycle, the gate of the FET is pulled low with 20mA, turning

it off.