LTC2925IGN datasheet(12/20 Pages) LINER

12 / 20 page

LTC2925

2925f

APPLICATIO S I FOR ATIO

3-Step Design Procedure

The following 3-step design procedure allows one to choose

the TRACK resistors, RTAx and RTBx, and the gate capaci-

tor, CGATE, that give any of the tracking or sequencing

profiles shown in Figures 1 to 4. A basic four supply appli-

cation circuit is shown in Figure 10.

Set the ramp rate of the master signal.

Solve for the value of CGATE, the capacitor on the GATE

pin, based on the desired ramp rate (V/s) of the master

supply, SM.

where I

GATE

=≈ µ

()

If the external FET has a gate capacitance comparable to

CGATE, then the external capacitor’s value should be re-

duced to compensate for the FET’s gate capacitance.

If no external FET is used, tie the GATE and RAMP pins

together, connect SENSEN and SENSEP to VCC, and con-

nect SCTMR to GND.

Solve for the pair of resistors that provide the desired

ramp rate of the slave supply, assuming no delay.

Choose a ramp rate for the slave supply, SS. If the slave

supply ramps up coincident with the master supply or with

a fixed voltage offset, then the ramp rate equals the master

supply’s ramp rate. Be sure to use a fast enough ramp rate

for the slave supply so that it will finish ramping before the

master supply has reached its final supply value. If not, the

slave supply will be held below the intended regulation

value by the master supply. Use the following formulas to

determine the resistor values for the desired ramp rate,

where RFB and RFA are the feedback resistors in the slave

supply and VFB is the feedback reference voltage of the

slave supply:

•( )

TRACK

′=

–

()

where VTRACK ≈ 0.8V.

Note that large ratios of slave ramp rate to master ramp

rate, SS/SM, may result in negative values for RTA´. If a

sufficiently large delay is used in step 3, RTA will be posi-

tive, otherwise SS/SM must be reduced.

Choose RTA to obtain the desired delay.

If no delay is required, such as in coincident and ratiometric

tracking, then simply set RTA = RTA´. If a delay is desired,

as in offset tracking and supply sequencing, calculate RTA´´

to determine the value of RTA where tD is the desired delay.

TRACK

′′ =

•

()

=′

′′

( )

the parallel combination of RTA´ and RTA´´

As noted in step 2, small delays and large ratios of slave

ramp rate to master ramp rate (usually only seen in se-

quencing) may result in solutions with negative values for

RTA. In such cases, either the delay must be increased or

the ratio of slave ramp rate to master ramp rate must be

reduced.

RSENSE

0.1

µF

10k

VCC SENSEP SENSEN

VIN

RONB

154k

VIN

RTB1

RTB2

RFA2

SLAVE2

MASTER

RFB2

RTA2

RTB3

RTA3

RTA1

RONA

100k

RAMPBUF

TRACK1

TRACK2

TRACK3

FB2

GATE

LTC2925

PGTMR

SDTMR

SCTMR

GND

2925 F10

RAMP

RFA3

SLAVE3

RFB3

DC/DC

OUT

DC/DC

RUN/SS

OUT

FB3

VIN

PGI

RFA1

SLAVE1

RFB1

SUPPLY

MONITOR

DC/DC

RUN/SS

OUT

FB1

FAULT

10k

VIN

STATUS

REMOTE

RST

SD3

SD2

SD1

CGATE

Ω

Figure 10. Four Supply Application

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