LTC2925

5

2925f

GND (Pin 10/Pins 7, 25): Circuit Ground.

TRACK1, TRACK2, TRACK3 (Pins 15, 14, 12/Pins 12, 11,

9): Tracking Control Input Pin. A resistive divider between

RAMPBUF, TRACKx and GND determines the tracking

profile of OUTx (see Applications Information). TRACKx

pulls up to 0.8V and the current supplied at TRACKx is

mirrored at FBx. The TRACKx pin is capable of supplying

supplying up to 10mA when the supply is at 5.5V, so care

should be taken not to short this pin for extended periods.

Limit the capacitance at the TRACKx pin to less than 25pF.

Float the TRACKx pins if unused.

FB1, FB2, FB3 (Pins 16, 13, 11/Pins 13, 10, 8): Feedback

Control Output. FBx connects to the feedback node of

slave supplies. Tracking is achieved by mirroring the

current from TRACKx into FBx. If the appropriate resistive

divider connects RAMPBUF and TRACKx, the FBx current

will force OUTx to track RAMP. The LTC2925 is capable of

controlling slave supplies with feedback voltages between

0V and 1.6V. To prevent damage to the slave supply, the

FBx pin will not force the slave’s feedback node above

2.5V. In addition, it will not actively sink current from this

node even when the LTC2925 is unpowered. Float the FBx

pins if unused.

REMOTE (Pin 17/Pin 14): Remote Sense Switch. A 15

Ω

switch connects REMOTE to RAMP when the GATE is fully

enhanced (GATE > RAMP + 4.9V). Otherwise, it presents

a high-impedance. When the slave supplies track the

master supply, REMOTE can be used to compensate for

the voltage drop across the external sense resistor and N-

channel FET. A resistor between the output and the sense

nodes of the master supply provides feedback before the

external FET is fully enhanced. If an external FET is not

used, float REMOTE.

RAMP (Pin 18/Pin15): Ramp Buffer Input. When the

RAMP pin is connected to the source of the external N-

channel FET, the slave supplies track the FET’s source as

it ramps up and down. Alternatively, when no external FET

is used, the RAMP pin can be tied directly to the GATE pin.

In this configuration, the supplies track the capacitor on

the GATE pin as it is charged and discharged by the 10

µA

current source controlled by the ON pin. When the GATE

is fully enhanced (GATE > RAMP + 4.9V) the open-drain

STATUS pin goes high-impedance and the remote sense

switch connects the RAMP pin to the REMOTE pin.

GATE (Pin 19/Pin 16): Gate Drive for External N-Channel

FET. When the ON pin is high, an internal 10

µA current

source charges the gate of the external N-channel MOSFET.

A capacitor connected from GATE to GND sets the ramp

rate. It is a good practice to add a 10

Ω resistor between

this capacitor and the FET’s gate to prevent high frequency

FET oscillations. An internal charge pump guarantees that

N-channel FETs are fully enhanced. When the ON pin is

pulled low, the GATE pin is pulled to GND with a 10

µA

current source. Under a short-circuit condition, the elec-

tronic circuit breaker in the LTC2925 pulls the GATE low

immediately with 20mA. Tie GATE to GND if unused.

FAULT (Pin 20/Pin 17): Circuit Breaker and Power Good

Timer Fault Output. FAULT is an open-drain output that

pulls low when the electronic circuit breaker is activated or

a power good timeout fault is detected. FAULT is reset by

pulling ON below 0.4V. To allow retry, tie FAULT to ON.

STATUS (Pin 21/Pin 18): Power Good Status Indicator.

The STATUS pin is an open-drain output that pulls low

until GATE has been fully charged at which time all

supplies will have reached their final operating voltage.

PGI (Pin 22/Pin 19): Power Good Timer Input. PGI con-

nects to the RST pin of the downstream supply monitor. If

PGI has not transitioned high within a power good timer

cycle (see PGTMR), the FAULT pin will be pulled low and

the supplies will be turned off by pulling the GATE pin low

with 20mA. PGI is pulled up with 10

µA. An internal

Float PGI when it is unused.

PGTMR (Pin 23/Pin 20): Power Good Timer. A capacitor

from PGTMR to GND sets the Power Good Timer duration.

10

µA. Otherwise, it pulls to GND. If the voltage on the

PGTMR pin exceeds 1.23V and PGI is still low, FAULT will

be pulled low and the GATE will be pulled to ground with

20mA until the power good timer fault is cleared by pulling

ON below 0.4V. If FAULT is tied back to ON the system will

automatically retry after a FAULT. In this mode, verify that

the slave supplies’ current limits provide sufficient protec-

tion under short-circuit conditions. Float PGTMR when it

is unused.