LTC2925

18

2925f

APPLICATIO S I FOR ATIO

defeating the tracking circuit (Figure 20). Often this delay

is intentionally configured by a soft-start capacacitor. This

can be remedied either by reducing the soft-start capacitor

on the slave supply or by increasing the shutdown timer

Layout Considerations

Be sure to place a 0.1

µF bypass capacitor as near as pos-

sible to the supply pin of the LTC2925.

To minimize the noise on the slave supplies’ outputs, keep

the traces connecting the FBx pins of the LTC2925 and the

feedback nodes of the slave supplies as short as possible.

In addition, do not route those traces next to signals with

fast transition times. In some circumstances it might be

MINIMIZE

TRACE

LENGTH

LTC2925

2925 F22

FB1

GND

0.1

µF

DC/DC

FB

OUT

Figure 21. Layout Considerations

Figure 22. Making PCB Connections to the Sense Resistor

IRC-TT SENSE RESISTOR

LR251201R010F

OR EQUIVALENT

0.01

Ω, 1%, 1W

CURRENT FLOW

TO LOAD

TO

SENSEP

TO

SENSEN

CURRENT FLOW

TO LOAD

TRACK WIDTH W:

0.03' PER AMP

ON 1 OZ COPPER

2925 F23

W

advantageous to add a resistor near the feedback node of

the slave supply in series with the FBx pin of the LTC2925.

This resistor must not exceed:

R

VV

I

V

V

RR

SERIES

FB

MAX

FB

FA

FB

== 





16

16

1

.–

.

–||

This resistor is most effective if there is already a capacitor

at the feedback node of the slave supply (often a compen-

sation component). Increasing the capacitance on a slave

supply’s feedback node will further improve the noise

immunity, but could affect the stability and transient re-

sponse of the supply.

For proper circuit breaker operation, Kelvin-sense PCB

connections between the sense resistor and the LTC2925’s

SENSEP and SENSEN pins are strongly recommended.

The drawing in Figure 22 illustrates the correct way of

making connections between the LTC2925 and the sense

resistor. PCB layout should be balanced and symmetrical

to minimize wiring errors. In addition, the PCB layout for

the sense resistor should include good thermal manage-

ment techniques for optimal sense resistor power

dissipation.

The power rating of the sense resistor should accommo-

date steady-state fault current levels so that the compo-

nent is not damaged before the circuit breaker trips.

1V/DIV

MASTER

SLAVE2

ON

SLAVE1

1ms/DIV

2925 F20

Figure 20. Power Supply Start-Ups Delayed