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TSB12C01APZ 数据表(PDF) 45 Page - Texas Instruments

部件名 TSB12C01APZ
功能描述  High-Speed Serial-Bus Link-Layer Controller
PDF  59 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TSB12C01APZ 数据表(HTML) 45 Page - Texas Instruments

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6–1
6 Parameter Measurement Information
tw1(L)
50%
50%
BCLK
tw1(H)
50%
tc1
Figure 6–1. BCLK Waveform
tsu1
tsu2
tsu3
tsu4
th1
th2
th3
th4
td1
td2
50%
50%
50%
50%
50%
50%
50%
BCLK
DATA0 – DATA31
ADDR0 – ADDR7
CA
(see Note A)
WR
CS
NOTE A: When back-to-back write cycles are done, a maximum of 9 BCLK cycles may be required after the falling edge
of CS before CA is asserted (low). DATA0 – DATA31, ADDR0 – ADDR7, and WR need to remain valid until
CA is asserted (low). These cycles are to synchronize data passing between the BCLK and SCLK clock
domains.
Figure 6–2. Host-Interface Write-Cycle Waveforms



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