TSB12C01APZ datasheet(22/59 Pages) TI

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3–6

Set

Clear

Clk

PhInt Bit

Interrupt Bit (INT)

Other

Interrupts

Interrupt Bit

IntMask Bit

PhInt Bit

PhIntMask Bit

INT

DATA (01)

PhInt Source

SCLK

Figure 3–2. Interrupt Logic Diagram Example

Table 3–4. Interrupt- and Mask-Register Field Descriptions

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Int

Interrupt

Int contains the value of all interrupt and interrupt mask bits ORed

together.

PhInt

Phy chip interrupt

When PhInt is set, the phy chip has signaled an interrupt through the

Phy interface.

PhyRRx

Phy register

information received

When PhyRRx is set, a register value has been transferred to the phy

chip access register (offset 24h) from the phy interface.

PhRst

Phy reset started

When PhRst is set, a phy-layer reconfiguration has started (1394 bus

reset).

Reserved

TxRdy

Transmitter ready

When TxRdy is set, the transmitter is idle and ready.

RxDta

Receiver has data

In normal mode and when set, RxDta indicates that the receiver has

accepted a quadlet of data into the GRF interface. This bit is set each

time a quadlet of data is accepted. However, during the self-ID portion

of a bus reset, this bit is set after each complete self-ID packet is

received into the GRF.

CmdRst

Command reset

received

When CmdRst is set, the receiver has been sent a quadlet write

request addressed to the RESET_START CSR register.

8–10

Reserved

ITStk

Transmitter is stuck

(IT)

When ITStk is set, the transmitter has detected invalid data at the

isochronous transmit-FIFO interface.

ATStk

Transmitter is stuck

(AT)

When ATStk is set, the transmitter has detected invalid data at the

asynchronous transmit-FIFO interface. If the first quadlet of a packet

is not written to the ATF_First or ATF_First&Update, the transmitter

enters a state denoted by an ATStuck interrupt. An underflow of the

ATF also causes an ATStuck interrupt. If this state is entered, no

asynchronous packets can be sent until the ATF is cleared by way of

the CLR ATF control bit. Isochronous packets can be sent while in this

state.

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