TSB12C01APZ datasheet(49/59 Pages) TI

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7–1

7 TSB12C01A to 1394 Phy Interface Specification

7.1

Introduction

This chapter provides an overview of a TSB12C01A to the phy interface. The information that follows can

be used as a guide through the process of connecting the TSB12C01A to a 1394 physical-layer device. The

part numbers referenced, the TSB11C01 and the TSB12C01A, represent the Texas Instruments

implementation of the phy (TSB11C01) and link (TSB12C01A) layers of the IEEE 1394-1995 standard.

The specific details of how the TSB11C01 device operates is not discussed in this document. Only those

parts that relate to the TSB12C01A phy-link interface are mentioned.

7.2

Assumptions

The TSB12C01A is capable of supporting 100 Mb/s, 200 Mb/s and 400 Mb/s phy-layer devices. For that

reason, this document describes an interface to a 400-Mb/s (actually 393.216-Mb/s) device. To support

lower-speed phy layers, adjust the width of the data bus by two terminals per 100 Mb/s. For example, for

100-, 200- and 400-Mb/s devices, the data bus is 2, 4, and 8 bits wide respectively. The width of the CTL

bus and the clock rate between the devices, however, does not change regardless of the transmission speed

that is used.

Finally, the 1394 phy layer has control of all bidirectional terminals that run between the phy layer and

TSB12C01A. The TSB12C01A can drive these terminals only after it has been given permission by the phy

layer. A dedicated request terminal (LREQ) is used by the TSB12C01A for any activity that the designer

wishes to initiate.

7.3

Block Diagram

The functional block diagram of the TSB12C01A to phy layer is shown in Figure 7–1.

ISO

D0 – D7

CTL0 – CTL1

LREQ

SCLK

1394

Link

Layer

1394

Phy-Layer

Device

TSB12C01A

NOTE A: See Table 2–2 for signal definition.

Figure 7–1. Functional Block Diagram of the TSB12C01A to Phy Layer

7.4

Operational Overview

The four operations that can occur in the phy-link interface are request, status, transmit, and receive. With

the exception of the request operation, all actions are initiated by the phy layer.

The CTL0 – CTL1 bus is encoded as shown in the following sections.

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