TSB12C01APZ datasheet(23/59 Pages) TI

23 / 59 page

3–7

Table 3–4. Interrupt- and Mask-Register Field Descriptions (Continued)

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Reserved

SntRj

Busy acknowledge

sent by receiver

When SntRj is set, the receiver is forced to send a busy acknowledge

to a packet addressed to this node because the GRF overflowed.

HdrEr

Header error

When HdrEr is set, the receiver detected a header CRC error on an

incoming packet that may have been addressed to this node.

TCErr

Transaction code

error

When TCErr is set, the transmitter detected an invalid transaction code

in the data at the transmit FIFO interface.

17 – 19

Reserved

CySec

Cycle second

incremented

When CySec is set, the cycle-second field in the cycle-timer register

is incremented. This occurs approximately every second when the

cycle timer is enabled.

CySt

Cycle started

When CySt is set, the transmitter has sent or the receiver has received

a cycle-start packet.

CyDne

Cycle done

When CyDne is set, an arbitration gap has been detected on the bus

after the transmission or reception of a cycle-start packet. This

indicates that the isochronous cycle is over.

CyPnd

Cycle pending

When CyPnd is set, the cycle-timer offset is set to 0 (rolled over or

reset) and remains set until the isochronous cycle ends.

CyLst

Cycle lost

When CyLst is set, the cycle timer has rolled over twice without the

reception of a cycle-start packet. This occurs only when this node is not

the cycle master.

CArbFI

Cycle arbitration

failed

When CArbFI is set, the arbitration to send the cycle-start packet failed.

26 – 30

Reserved

IArbFI

Isochronous

arbitration failed

When IArbFI is set, the arbitration to send an isochronous packet failed.

3.2.5

Cycle-Timer Register

The cycle-timer register contains the seconds_count, cycle_count and cycle_offset fields of the cycle timer.

The register is at address 14h and is read/write. This field is controlled by the cycle master, cycle source,

and cycle timer enable bits of the control register. Its initial value is 0000_0000h.

Table 3–5. Cycle-Timer Register Field Descriptions

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

0–6

seconds_count

Seconds count

1-Hz cycle-timer counter

7–19

cycle_count

Cycle count

8,000-Hz cycle-timer counter

20 – 31

cycle_offset

Cycle offset

24.576-MHz cycle-timer counter

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