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TSB12C01APZ 数据表(PDF) 18 Page - Texas Instruments |
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TSB12C01APZ 数据表(HTML) 18 Page - Texas Instruments |
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18 / 59 page ![]() 3–2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31 00h Interrupt ATAck PhyRgAd PhyRxAd Version Node Address Control Reserved Cycle Timer Interrupt Mask Isoch Port Number Diagnostics Phy Chip Access Reserved Reserved ATF Status ITF Status Reserved GRF Status Reserved BlkBusDep 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 28 7 Bits IR Port1 Seconds Count BsyCtrl Bus Number TAG TAG Rollover @ 8000 Cycle Count 13 Bits Rollover @ 3072 12 Bits IR Port2 Node Number Version PhyRgData Revision Cycle Offset PhyRxData Size Size Size NOTE A: All gray areas (bits) are reserved bits. Figure 3–1. Internal Register Map 3.2.1 Version/Revision Register The version/revision register allows software to be written that supports multiple versions of the high-speed serial-bus link-layer controllers. This register is at address 00h and is read only. The initial value is 3031_3041h. |
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