TSB12C01APZ datasheet(15/59 Pages) TI

15 / 59 page

2–3

CYCLEOUT indicates to the cyclemaster node that it is time to send a cycle-start packet. And, on

noncyclemaster nodes, CYCLEOUT indicates that it is time to expect a cycle-start packet. The cycle-start

bit is set when the cycle-start packet is sent from the cyclemaster node or received by a noncyclemaster

node.

2.1.6

Cycle Monitor

The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes

chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,

the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the

cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the

cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the

cycle-master bit is set in the control register.

2.1.7

Cyclic Redundancy Check (CRC)

The CRC module generates a 32-bit CRC for error detection. This is done for both the header and data. The

CRC module generates the header and data CRC for transmitting packets and checks the header and data

CRC for received packets. See the IEEE 1394-1995 standard for details on the generation of the CRC†.

2.1.8

Internal Registers

The internal registers control the operation of the TSB12C01A. The register definitions are specified in

Section 3.

2.1.9

Host Bus Interface

The host bus interface allows the TSB12C01A to be easily connected to most host processors. This host

bus interface consists of a 32-bit data bus and an 8-bit address bus. The TSB12C01A utilizes cycle-start

and cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be

asynchronous to one another. The TSB12C01A is interrupt driven to reduce polling.

† This is the same CRC used by the IEEE802 LANs and the X3T9.5 FDDI.

TSB12C01APZ 数据表(PDF) 15 Page - Texas Instruments