TSB12C01APZ datasheet(28/59 Pages) TI

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3–12

3.3.2

ATF Access

The procedure to access to the ATF is as follows:

Write the first quadlet of the packet to ATF location 80h: the data is not confirmed for transmission.

Write the second n–1 quadlets of the packet to ATF location 84h: the data is not confirmed for

transmission.

Write the final quadlet of the packet to ATF location 8Ch: the data is confirmed for transmission.

If the first quadlet of a packet is not written to the ATF_First address, the transmitter enters a state

denoted by an ATStuck interrupt. An underflow of the ATF also causes an ATStuck interrupt.

When this state is entered, no asynchronous packets can be sent until the ATF is cleared via the

CLR ATF control bit. Isochronous packets can be sent while in this state.

Ack code = 0000b is reserved, however, the TSB12C01A uses ATAck code = 0000b to indicate

that no acknowledgement was received. For example, if an asynchronous write is addressed to a

nonexistent address, the TSB12C01 waits until a time out occurs and then sets ATAck (in the

node address register) to 0000b. After the asychonous command is sent, the sender reads

ATAck. If ATAck = 0000b, then a time out has occurred (i.e., no response from any node was

received).

ATF access example:

The first quadlet of n quadlets is written to ATF location 80h. Quadlets (2 to n-1) are written to ATF

location 84h. The last quadlet (nth) is written to ATF location 8Ch. If the ATFEmpty bit is true, it is

set to false and the TSB12C01A requests the phy layer to arbitrate for the bus. To ensure that an

ATF underflow condition does not occur, loading of the ATF in this manner is suggested.

After loading the ATF with an asychronous packet and sending it, the software driver needs to

wait until the TxRdy bit (bit 5) of the Interrupt register is set to 1 before reading ATAck. When

TxRdy is set to 1, this indicates that the transmitter has received an ACK or time out. So the

correct ATAck can then be read from the node address register. In order to receive the next Ack

code, the TxRdy bit needs to be cleared to 0.

3.3.3

ITF Access

The procedure to access to the ITF is as follows:

Write to ITF location 90h: the data is not confirmed for transmission (first quadlet of the packet).

Write to ITF location 94h: the data is not confirmed for transmission (second n–1 quadlets of the

packet).

Write to ITF location 98h: the data is confirmed for transmission (first quadlet of the packet). The

read logic sees all data written to the FIFO since the last confirm (update).

Write to ITF location 9Ch: the data is confirmed for transmission (second n quadlet of the packet).

If the first quadlet of a packet is not written to the ITF_First or ITF_First&Update, the transmitter

enters a state denoted by an ITStuck interrupt. An underflow of the ITF also causes an ITStuck

interrupt. When this state is entered, no isochronous packets can be sent until the ITF is cleared

by the CLR ITF control bit. Asynchronous packets can be sent while in this state.

ITF access example:

The first quadlet of n quadlets is written to ITF location 90h. Quadlets (2 to n-1) are written to ITF

location 94h. The last quadlet (nth) is written to ITF location 9Ch. If the ITFEmpty is true, it is set to

false and the TSB12C01A requests the phy layer to arbitrate for the bus. To ensure that an ITF

underflow condition does not occur, loading of the ITF in this manner is suggested.

3.3.4

General-Receive-FIFO (GRF)

Access to the GRF is done with a read from the GRF, which requires a read from address C0h.

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