AD8363ACPZ-R7 datasheet(28/36 Pages) AD

28 / 36 page

AD8363

Rev. 0 | Page 28 of 36

When VSET is set to a particular value, the AD8363 compares

this value to the equivalent input power present at the RF input.

If these two values do not match, VOUT increases or decreases in

an effort to balance the system. The dominant pole of the error

amplifier/integrator circuit that drives VOUT is set by the capacitance

on the CLPF pin; some experimentation may be necessary to

choose the right value for this capacitor.

In general, CLPF should be chosen to provide stable loop operation

for the complete output power control range. If the slope (in

dB/V) of the gain control transfer function of the VGA is not

constant, CLPF must be chosen to guarantee a stable loop when

the gain control slope is at its maximum. In addition, CLPF must

provide adequate averaging to the internal low range squaring

detector so that the rms computation is valid. Larger values of CLPF

tend to make the loop less responsive.

The relationship between VSET and the RF input follows the

measurement mode behavior of the device. For example, Figure 6

shows the measurement mode transfer function at 900 MHz

and that an input power of −10 dBm yields an output voltage

of approximately 2.5 V. Therefore, in controller mode, if VSET is

2.5 V, the AD8363 output would go to whatever voltage is

necessary to set the AD8363 input power to −10 dBm.

CONSTANT OUTPUT POWER OPERATION

In controller mode, the AD8363 can be used to hold the output

power of a VGA stable over a broad temperature/input power

range. This is useful in topologies where a transmit card is driving

an HPA, or when connecting any two power sensitive modules

together. Figure 66 shows a schematic of a circuit setup that holds

the output power to approximately −26 dBm at 2.14 GHz, when

the input power is varied over a 40 dB dynamic range. Figure 67

shows the results. A portion of the output power is coupled off

using a 10 dB coupler, and it is then fed into the AD8363. VSET is

fixed at 0.95 V, which forces to AD8363 output voltage to control

the ADL5330 so that the input to the AD8363 is approximately

−36 dBm. If the AD8363 was in measurement mode and a

−36 dBm input power is applied, the output voltage would be

0.95 V. A general-purpose, rail-to-rail op amp (AD8062) is used

to invert the slope of the AD8363 so that the gain of the ADL5330

decreases as the AD8363 control voltage increases. The output

power is controlled to a 10 dB higher power level than that seen

by the AD8363 due to the coupler. The high end power is

limited by the linearity of the VGA (ADL5330) with high

attenuation and can be increased by using a higher linearity VGA.

The low end power is limited by the maximum gain of the VGA

(ADL5330) and can be increased by using a VGA with more

gain. The temperature performance is directly related to the

temperature performance of the AD8363 at 2.14 GHz and

−26 dBm, using TCM1 = 0.52 V and TCM2 = 0.6 V. All other

temperature variations are removed by the AD8363.

For more information on controller mode, see the Controller

Mode Basic Connections section.

100pF

C11

100pF

C12

100pF

C10

0.1µF

C12

0.1µF

INHI

INLO

OPHI

OPLO

GAIN

ADL5330

POUT

10dB

COUPLER

AD8062

10k

Ω

10k

Ω

10k

Ω

10k

Ω

0.95V

0.6V

0.52V

INHI

TCM1

TCM2

VSET

VOUT

CLPF

INLO

AD8363

Figure 66. Constant Power Circuit

–25.0

–25.5

–26.0

–26.5

–27.0

–27.5

–28.0

–40

–35

–30

–25

–20

–15

–10

–5

PIN (dBm)

–20°C

–40°C

+85°C

+25°C

0°C

Figure 67. Performance of the Circuit Shown in Figure 66

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